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Xilinx Virtex-7 FPGA VC7203 - Page 33

Xilinx Virtex-7 FPGA VC7203
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VC7203 IBERT Getting Started Guide www.xilinx.com 33
UG847 (v3.0) July 10, 2013
Creating the GTX IBERT Core
10. Back to Manage IP, in the Sources window, right-click the IBERT IP and select Open IP
Example Design (Figure 1-27). Specify a location to save the design, press OK, and the
design opens in a new Vivado design tools window.
X-Ref Target - Figure 1-26
Figure 1-26: Customize IP - Clock Settings
8*BFBB

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