Xilinx Virtex-7 FPGA VC7203 User Manual

VC7203 IBERT Getting Started Guide www.xilinx.com 33
UG847 (v3.0) July 10, 2013
Creating the GTX IBERT Core
10. Back to Manage IP, in the Sources window, right-click the IBERT IP and select Open IP
Example Design (Figure 1-27). Specify a location to save the design, press OK, and the
design opens in a new Vivado design tools window.
X-Ref Target - Figure 1-26
Figure 1-26: Customize IP - Clock Settings
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Xilinx Virtex-7 FPGA VC7203 Specifications

General

FPGA Family	Virtex-7
Device	XC7VX485T
Transceivers	16
Maximum Transceiver Speed	12.5 Gbps
Transceiver Type	GTX
DSP Slices	2, 800
Block RAM	37, 080 KB
Clock Management Tiles	12
PCIe Gen2/Gen3 Support	Yes
Package	FFG1761