EasyManua.ls Logo

Xilinx Virtex-7 FPGA VC7203 - Page 38

Xilinx Virtex-7 FPGA VC7203
46 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
38 www.xilinx.com VC7203 IBERT Getting Started Guide
UG847 (v3.0) July 10, 2013
Chapter 1: VC7203 IBERT Getting Started Guide
14. Synthesize the partitioned IBERT core only. To do this, right-click the IBERT synthesis
run in the Design Runs window under Module Analysis Runs and select Launch
Runs (Figure 1-31). In the Launch Selected Runs window, leave the defaults
unchanged and click OK.
15. When the synthesis is done, click Run Synthesis in the Flow Navigator, which
synthesizes the rest of the design.
16. When that synthesis is done, a Synthesis Complete window pops up. Select Open
Synthesized Design and click OK (Figure 1-32).
X-Ref Target - Figure 1-31
Figure 1-31: Synthesize IBERT Partition
8*BFBB

Related product manuals