Xilinx Virtex-7 FPGA VC7203 - Page 40

40 www.xilinx.com VC7203 IBERT Getting Started Guide
UG847 (v3.0) July 10, 2013
Chapter 1: VC7203 IBERT Getting Started Guide
18. In the Flow Navigator under Program and Debug, click Generate Bitstream
(Figure 1-34). A window pops up asking if it is ok to launch implementation. Click
Yes.
X-Ref Target - Figure 1-33
Figure 1-33: Debug Core Options for dbg_hub
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