Yamaha A5000 - Lsi Pin Description

A5000/A4000
10
LSI PIN DESCRIPTION
(IC507)TC203C760HF-002 (XS725A00) SWP30B (AWM Tone Generator coped with MEG) Standard Wave Processor
PIN
NO.
NAME I/O FUNCTION
PIN
NO.
NAME I/O FUNCTION
1Vss
(
Ground
)
121 VSS -
(
Ground
)
2 CA0 I 122 HMD0 I/O
3 CA1 I 123 HMD1 I/O
4 CA2 I 124 HMD2 I/O
5 CA3 I 125 HMD3 I/O
6 CA4 I 126 HMD4 I/O
7 CA5 I Address bus of internal re
g
ister 127 HMD5 I/O
8 CA6 I 128 HMD6 I/O Wave memor
y
data bus
(
Upper 16 bits
)
9 CA7 I 129 HMD7 I/O
10 CA8 I 130 HMD8 I/O
11 CA9 I 131 HMD9 I/O
12 CA10 I 132 HMD10 I/O
13 CA11 I 133 HMD11 I/O
14 VSS -
(
Ground
)
134 HMD12 I/O
15 CD0 I/O 135 HMD13 I/O
16 CD1 I/O 136 HMD14 I/O
17 CD2 I/O 137 HMD15 I/O
18 CD3 I/O 138 VSS -
(
Ground
)
19 CD4 I/O 139 HMA0 O
20 CD5 I/O 140 HMA1 O
21 CD6 I/O 141 HMA2 O
22 CD7 I/O 142 HMA3 O
23 CD8 I/O Data bus of internal re
g
ister 143 HMA4 O
24 CD9 I/O 144 HMA5 O
25 CD10 I/O 145 HMA6 O
26 CD11 I/O 146 HMA7 O
27 CD12 I/O 147 HMA8 O
28 CD13 I/O 148 HMA9 O
29 CD14 I/O 149 HMA10 O
30 VDD - (Power supply) 150 VDD - (Power supply)
31 VSS - (Ground) 151 VSS - (Ground)
32 CD15 I/O 152 HMA11 O
33 CSN I Chip select 153 HMA12 O Wave memor
y
address bus
34 WRN I Write strobe 154 HMA13 O
35 RDN I Read strobe 155 HMA14 O
36 VDD -
(
Power suppl
y)
156 HMA15 O
37 SYSH0 O 157 HMA16 O
38 SYSH1 O 158 HMA17 O
39 SYSH2 O 159 HMA18 O
40 SYSH3 O NSYS/LNSYS upper 16 bits output 160 HMA19 O
41 SYSH4 O 161 HMA20 O
42 SYSH5 O 162 HMA21 O
43 SYSH6 O 163 HMA22 O
44 SYSH7 O 164 HMA23 O
45 KONO0 O 165 HMA24 O
46 KONO1 O Ke
y
on data 166 VSS -
(
Ground
)
47 KONO2 O 167 MRASN O
RAS when DRAM
(
s
)
is connected to wave memor
y
48 KONO3 O 168 MCASN O
CAS when DRAM
(
s
)
is connected to wave memor
y
49 VSS -
(
Ground
)
169 MOEN O Wave memor
y
output enable
50 SYSL0 I/O 170 MWEN O Wave memor
y
write enable
51 SYSL1 I/O 171 VSS -
(
Ground
)
52 SYSL2 I/O 172 LMD0 I/O
53 SYSL3 I/O NSYS input/LNSYS output lower 8 bits 173 LMD1 I/O
54 SYSL4 I/O 174 LMD2 I/O
55 SYSL5 I/O 175 LMD3 I/O
56 SYSL6 I/O 176 LMD4 I/O
57 SYSL7 I/O 177 LMD5 I/O
58 KONI0 I 178 LMD6 I/O
59 KONI1 I Key on data input 179 LMD7 I/O Wave memory data bus (Lower 16 bits)
60 VDD - (Power supply) 180 VDD - (Power supply)
61 VSS - (Ground) 181 VSS - (Ground)
62 KONI2 I 182 LMD8 I/O
63 KONI3 I 183 LMD9 I/O
64 DAC0 O DAC output 184 LMD10 I/O
65 DAC1 O 185 LMD11 I/O
66 W CLK O DAC0/DAC1 word clock 186 LMD12 I/O
67 MELO0 O 187 LMD13 I/O
68 MELO1 O 188 LMD14 I/O
69 MELO2 O 189 LMD15 I/O
70 MELO3 O MEL wave data output 190 VSS -
(
Ground
)
71 MELO4 O 191 LMA0 O
72 MELO5 O 192 LMA1 O
73 MELO6 O 193 LMA2 O
74 MELO7 O 194 LMA3 O
75 VDD -
(
Power suppl
y)
195 LMA4 O
76 ADLR O ADC word clock 196 LMA5 O
77 MELI0 I 197 LMA6 O
78 MELI1 I 198 LMA7 O
79 MELI2 I 199 LMA8 O
80 MELI3 I MEL wave data input 200 LMA9 O
81 MELI4 I 201 LMA10 O
82 MELI5 I 202 LMA11 O
83 MELI6 I 203 VSS -
(
Ground
)
84 MELI7 I 204 LMA12 O
85 VSS -
(
Ground
)
205 LMA13 O Wave memor
y
address bus
(
Lower data memor
y)
86 RCASN O DRAM column address strobe
(
RAS si
g
nal
)
206 LMA14 O
87 RA8 O 207 LMA15 O
88 RA7 O 208 LMA16 O
89 RA6 O 209 LMA17 O
90 VDD - (Power supply) 210 VDD - (Power supply)
91 VSS - (Ground) 211 VSS - (Ground)
92 RA5 O DRAM address bus 212 LMA18 O
93 RA4 O 213 LMA19 O
94 RA3 O 214 LMA20 O
95 RA2 O 215 LMA21 O
96 RA1 O 216 LMA22 O
97 RA0 O 217 LMA23 O
98 RRASN O DRAM row address strobe
(
RAS si
g
nal
)
218 LMA24 O
99 RWEN O DARM write enable 219 VSS -
(
Ground
)
100 VSS -
(
Ground
)
220 SYO O S
y
nc. si
g
nal for master clock
101 RD7 I/O 221 SYOD O S
y
nc. si
g
nal for HCLK/QCLK
102 RD6 I/O 222 QCLK O 1/12 master clock
(
64Fs
)
103 RD5 I/O 223 HCLK O 1/6 master clock
(
128Fs
)
104 RD4 I/O 224 CK256 O 1/3 master clock
(
256Fs
)
105 RD3 I/O 225 SYSCLK O 1/2 master clock
(
384Fs
)
106 RD2 I/O 226 VDD -
(
Power suppl
y)
107 RD1 I/O 227 SYI I S
y
nc. clock
108 RD0 I/O 228 MCLKI I Master clock input
109 VSS -
(
Ground
)
229 MCLKO O Master clock output
110 RD17 I/O 230 VDD -
(
Power suppl
y)
111 RD16 I/O DRAM data bus 231 XIN I Cr
y
stal osc. input
112 RD15 I/O 232 XOUT O Cr
y
stal osc. output
113 RD14 I/O 233 VSS -
(
Ground
)
114 RD13 I/O 234 ICN I Initial clear
115 RD12 I/O 235 CHIP2 I 2 chips mode enable
116 RD11 I/O 236 SLAVE I Master/Slave select when 2 chips mode
117 RD10 I/O 237 TESTON I
118 RD9 I/O 238 ACIN I Test pin
119 RD8 I/O 239 DCTEST I
120 VDD -
(
Power suppl
y)
240 VDD -
(
Power suppl
y)