Zenith H-100 - Page 49

Upon DRQ becoming active, an additional delay is needed
to fulfill the access time requirements of the 1797
Controller. The access delay and synchronization to the
S-100 Bus are both accomplished by counting system clocks.
An on-board jumper selects whether one system clock is
counted (for systems with clocks up to 3 MHz) or two system
clocks are coun ted (for systems with clocks up to 6 MHz).
For 0 per at ion a tIe sst han 3 MHz, j urn per J 1 (n ear U19 )
should be jumpered between F and G. For operation between
3 and 6 MHz, this jumper should be between F and E (normal
position for the H/Z-100).
At the completion of the access delay, the wait state is
cleared. RDY is asserted, and the CPU completes the read
or wr i te of the data reg ister in the 1797. A RESET or an
INTRQ signal also clears the wait state, so that the CPU
does not hang up after an error during a disk access.
WRITE COMMAND REGISTER IN THE 1797 (U22)
The command register in the 1797 can be written when AO,
A1, and A2 are all low. The FDWR signal at U22-2 is
asserted when both FDEN and pWR* are logic zero. The signal
pWR comes directly from the CPU, while FDEN is a composite
signal made up of FDSEL and U26-5. The output of U26-5
is the signal that starts the access of the 1797 controller
at the end of the wait state.
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