Zenith H-100 - Page 7

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PROCESSOR SWAP PORT
OVERVIEW
The processor swap port controls which CPU is to be active,
handles interrupt routing, and ensures proper timing of
the clock circuits during the swap. To access the swap
port, the CPU writes a control byte to port OFEH. Only
three bits of the byte are used: ADO controls the interrupt
mask, ADl controls the swap interrupt line, and AD7 performs
the processor swap.
PROCESSOR SWAP
Refer to schematic MBl as you read the following.
At power up, the reset circuits clear U171-9 to logic zero.
This pin, 8SEL, connects to U186-5, a 12H6 PAL. This IC
responds by placing a logic zero on U181-12 and a l~c
one on U181-2. On the first positive transition of 85~,
the 85HOLD line will go low, enabling the 8085 CPU. On
the first positive transition of ~, the 88HOLD line will
go high, disabling the 8088 cpu.
The 8085, while executing the code in the monitor ROM, soon
transfers control to the 8088. It does this by setting
bit 7 of the processor swap port control byte to logic one.
Here's how .•.
The CPU addresses port OFEH to assert SWAPCS (from the 1/0
decoder) at U206-5. It then sets AD7 to logic one at
U111-12. Finally, it asserts the write line at U206-6.
As a result, Ul11-11 goes high and latches U171-9 to logic
one. The 8SEL line is now asserted.
The values at U172-12 and U172-2 are also latched to their
respective outputs, but these will be covered later.
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