Zenith H-100 - Page 8

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The 8SEL line. now logic one. causes U186-13 to change to
logic one. U186-18 to change to logic zero. and U186-16
to change to logic one.
The HOLD. line at U185-11 asserts whenever a board on the
S-100 bus takes control of the H/Z-100. This causes U186
to disable both the 8085 and the 8088 through U187. Both
CPUs respond by returning their hold-acknowledge signals;
the 8088 at U186-3 and the 8085 at U171-2. When this
happens. U186 asserts the HAK line at pin 17. This, in
turn, raises the S-100 pHLOA line to logic one at U180-9.
The board that generated the HOLD· request can now take
control of the H/Z-100.
SWAP TIMING
The 88SEL line also goes to U188-4, a quad D-type latch.
This circuit is designed to suppress any glitches on the
system clock line when the H/Z-100 switches from one CPU
to the other. It also ensures that the CPU being disabled
is no longer active when the other CPU is enabled.
The 8085 and the 8088 run on separate crystal-controlled
clocks; the 8085 from Y101 and the 8088 from Y103. Although
these clocks are stable. they aren't in phase. Switching
from one clock to another can cause a glitch on the system
clock line, S~. which can upset the timing in other
circuits.