ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
125
CPDR
Compare and Decrement with Repeat
Operation
repeat {
A–(HL)
HL ← HL – 1
BC ← BC – 1
} while (~Z and BC ≠ 0)
Description
The CPU compares the contents of the accumulator, A, to the memory location that the
HL register points to and outputs the difference. This instruction does not affect the con-
tents of the reference memory location or the accumulator. The HL and BC registers dec-
rement. This operation is repeated until one of the following two conditions is met:
1. A = (HL), which sets the 0 Flag (Z).
2. BC is decremented to 0, which resets the P/V Flag.
In Z80 mode, the BC register is 16 bits, which allows the CPDR instruction to repeat a
maximum of 65536 (64 K) times. In ADL mode, the BC register is 24 bits, which allows
the CPDR instruction to repeat a maximum of 16,777,216 (16 M) times.
Condition Bits Affected
Attributes
S Set if result is negative; reset otherwise.
Z Set if A = (HL); reset otherwise.
H Set if borrow from bit 4; reset otherwise.
P/V Set if BC – 1 ≠ 0; reset otherwise.
N Set.
C Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
CPDR —X 1 + 3 * BCED, B9
CPDR.S —1 2 + 3 * BC52, ED, B9
CPDR.L —0 2 + 3 * BC49, ED, B9

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English