eZ80
®
CPU
User Manual
UM007714-0908 Interrupts
43
Vectored Interrupts for On-Chip Peripherals
Vectored interrupts operate in the same manner as Mode 2 interrupts, irrespective of which
interrupt mode is selected. In the case of the vectored interrupts, the CPU does not fetch
the low-order interrupt vector address from the data bus, D[7:0]. Instead, the CPU fetches
from the internal vectored interrupt bus, at address IVECT[8:0]. The internal vectored
interrupt bus is used exclusively for on-chip peripherals.
Z80 Mode 0 1
Read the LSB of the interrupt vector placed on the data bus,
D[7:0], bus by the interrupting peripheral.
•
IEF1
←
0
•
IEF2
←
0
•
The starting Program Counter is effectively {MBASE,
PC[15:0]}.
•
Push the 2-byte return address, PC[15:0], onto the SPL
stack.
•
Push a 00h byte onto the SPL stack to indicate an interrupt
from Z80 mode (because ADL = 0).
•
Set the ADL mode bit to 1.
•
The interrupt vector address is located at { I[15:0], D[7:0]
}.
•
PC[23:0] ←
( { I[15:0], D[7:0] } )
.
•
The ending Program Counter is { PC[23:0] }.
•
The interrupt service routine must end with RETI.L
ADL Mode 1 1
Read the LSB of the interrupt vector placed on the data bus,
D[7:0], by the interrupting peripheral.
•
IEF1
←
0
•
IEF2
←
0
•
The starting Program Counter is PC[23:0].
•
Push the 3-byte return address, PC[23:0], onto the SPL
stack.
•
Push a 01h byte onto the SPL stack to indicate a restart
from ADL mode (because ADL = 1).
•
The ADL mode bit remains set to 1.
•
The interrupt vector address is located at {00h, I[7:0],
D[7:0]}.
•
PC[23:0] ←
( { I[15:0], D[7:0] } )
.
•
The ending Program Counter is { PC[23:0] }.
•
The interrupt service routine must end with RETI.L
Table 24. Interrupt Mode 2 Operation (Continued)
Memory Mode
ADL
Bit
MADL
Bit Operation
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