ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
59
Instruction Summary
Table 37 describes each type or class of instruction, using the notation described in the
preceding sections. In addressing modes where the same location acts as both the
destination (Dest) and the source (Source), the information is centered between the Dest
and Source columns (for example, the
DEC instruction). The instruction summary table is
sorted alphabetically by the assembly language mnemonics.
Table 37. Instruction Summary
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
ADC A,s
A ←
A+s+C
(HL) 8E *** V 0*
ir DD/FD 8C–8D
(IX/Y+d) DD/FD 8E dd
n CE
r 88–8F
ADC HL,ss
HL ←
HL+ss+C
rr ED 4A–6A *** V 0*
SP ED 7A
ADD A,s
A ←
A+s
(HL) 86 *** V 0*
ir DD/FD 84–85
(IX/Y+d) DD/FD 86 dd
n C6
r 80–87
ADD HL,ss
HL ←
HL+ss
rr 09–29 —— * — 0 *
SP 39
ADD IX/Y,ss
IX/Y ←
IX/y+ss
rxy DD/FD 09–29 —— * — 0 *
SP DD 39
AND A,s
A ←
A AND s
(HL) A6 **1 P 00
ir DD/FD A4–A5
(IX/Y+d) DD/FD A6 dd
n E6
r A0–A7
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English