eZ80
®
CPU
User Manual
UM007714-0908 Memory Mode Switching
25
The assembled prefix bytes replace Z80 and Z80180 instructions that do not offer a func-
tion. If an CPU assembler encounters one of these replaced instructions, it issues a warn-
ing message and assembles it as a standard NOP (
00h). The CPU prefix bytes are
indicated in Table 13.
For the traditional Z80 prefix bytes, the CPU does not allow an interrupt to occur in the
time between fetching one of these prefix bytes and fetching the following instruction.
The traditional Z80 prefix bytes are
CBh, DDh, EDh, and FDh, which indicate opcodes that
are not on the first page of the opcode map. The eZ80
®
MEMORY mode prefix bytes
(
40h, 59h, 52h, 5Bh) must precede the traditional Z80 prefix bytes.
Persistent Memory Mode Changes in ADL and Z80 Modes
The CPU can only make persistent mode switches between ADL mode and Z80 mode as
part of a special control transfer instruction (CALL, JP, RST, RET, RETI, or RETN), or
as part of an interrupt or trap operation. The Program Counter (PC) is thus prevented from
making an uncontrolled jump. When the memory mode is changed in any of these ways, it
remains in its new state until another of these operations changes the mode back. Persis-
tent mode changes are ideal for calling and executing a block of Z80-style code from
within a higher-level ADL mode program. Memory mode switching, using interrupts, and
traps are discussed in later sections of this manual.
Table 12. CPU Code Suffix to Assembled Prefix Mapping
CPU Code Suffix
Assembled Prefix Byte
(hex)
.SIS 40
.LIS 49
.SIL 52
.LIL 5B
Table 13. Z80 Instructions Replaced by Memory Mode Suffixes
Opcode Prefix
(hex)
Previous Z80 and Z180
Instruction New CPU Suffix
40 LD B,B .SIS
49 LD C,C .LIS
52 LD D,D .SIL
5B LD E,E .LIL
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