eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
153
IN0 r, (n)
Input from I/O
Operation
r ← ({UU, 00h, n})
Description
The
n
operand is placed on the lower byte of the address bus, ADDR[7:0], while the High
byte of the address bus, ADDR[15:8], is forced to 0. The upper byte of the address bus,
ADDR[23:16] is undefined for I/O addresses.The byte at this I/O address is written to the
specified register
r (A, B, C, D, E, H, or L).
Condition Bits Affected
Attributes
jj identifies the A, B, C, D, E, H, or L register and is assembled into one of the opcodes
indicated in Table 55.
S Set if byte is negative; reset otherwise.
Z Set if byte is 0; reset otherwise.
H Reset.
P/V Set if parity is even; reset otherwise.
N Reset.
C Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
IN0 r,(n)X 4ED, jj, nn
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