ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
177
INIR
Input from I/O and Increment with Repeat
Operation
repeat {
(HL) ← ({UU, BC[15:0]})
B ← B – 1
HL ← HL+1
} while B ≠ 0
Description
The CPU places the contents of BC[15:0] onto the lower two bytes of the address bus,
ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O
addresses. The CPU reads the byte located at I/O address {UU, BC[15:0]} into CPU mem-
ory. The CPU next places the contents of HL onto the address bus and writes the byte to
the memory address specified by the HL register. The B register decrements and the HL
register increments. Next, the CPU sets the Z Flag to 1 if the B register decrements to 0.
The instruction repeats until the B register equals 0.
Condition Bits Affected
Attributes
S Not affected.
Z Set if B – 1 = 0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is a logical 1; reset otherwise.
C Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
INIR —X 2 + 3 * BED, B2
INIR.S —1 3 + 3 * B52, ED, B2
INIR.L —0 3 + 3 * B49, ED, B2

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English