ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
274
OUTI2
Output to I/O and Increment
Operation
({UU, BC[15:0]}) ← (HL)
B ← B – 1
C ← C+1
HL ← HL+1
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The
upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B regis-
ter decrements. The C and HL registers increment.
Condition Bits Affected
Attributes
S Not affected.
Z Set if B – 1 = 0; reset otherwise.
H Not affected.
P/V Not affected.
N Set if msb of data is logical 1; reset otherwise.
C Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
OUTI2 —X 5ED, A4
OUTI2.S —1 652, ED, A4
OUTI2.L —0 649, ED, A4

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English