eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
278
POP IX/Y
Pop Stack
Operation
if ADL mode {
IX/Y[7:0] ← (SPL)
IX/Y[15:8] ← (SPL+1)
IX/Y[23:16] ← (SPL+2)
SPL ← SPL+3
}
else Z80 mode {
IX/Y[7:0] ← (SPS)
IX/Y[15:8] ← (SPS+1)
SPS ← SPS+2
}
Description
In ADL mode, or when the
.L
suffix is employed, 3 bytes are popped off the stack begin-
ning at the memory location specified by SPL. The first byte popped off the stack from
SPL is written to the Low byte of the specified Index Register, IXL or IYL. The second
byte popped off the stack from (SPL+1) is written to the High byte of the specified Index
Register, IXH or IYH. The third byte popped off the stack from (SPL+2) is written to the
upper byte of the specified Index Register, IXU or IYU. The SPL increments by 3.
In Z80 mode, or when the
.S
suffix is employed, the first 2 bytes are popped off the stack
beginning at the memory location specified by SPS. The first byte popped off the stack
from (SPS+1) is written to the Low byte of the specified Index Register, IXL or IYL. The
second byte popped off the stack from (SPS+2) is written to the High byte of the specified
Index Register, IXH or IYH. The SPS increments by 2.
Condition Bits Affected
None.
Attributes
Mnemonic Operand ADL Mode Cycle Opcode (hex)
POP IX 0/1 4/5 DD, E1
POP.S IX 1 5 52, DD, E1
POP.L IX 0 6 49, DD, E1
POP IY 0/1 4/5 FD, E1
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