ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 CPU Instruction Set
280
POP rr
Pop Stack
Operation
if ADL mode {
rr[7:0]← (SPL)
rr[15:8]← (SPL+1)
rr[23:16]← (SPL+2)
SPL ← SPL+3
}
else Z80 mode {
rr[7:0]← (SPS)
rr[15:8]← (SPS+1)
SPS ← SPS+2
}
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL.
In ADL mode, or when the
.L suffix is employed, 3 bytes are popped off the stack begin-
ning at the memory location specified by SPL. The first byte popped off the stack from
SPL is written to the Low byte of the specified register,
rr [7:0]. The second byte popped
off the stack from (SPL+1) is written to the High byte of the specified register,
rr [15:8].
The third byte popped off the stack from (SPL+2) is written to the upper byte of the speci-
fied register,
rr [23:16]. The SPL increments by 3.
In Z80 mode, or when the
.S suffix is employed, the first 2 bytes are popped off the stack
beginning at the memory location specified by SPS. The first byte popped off the stack
from (SPS+1) is written to the Low byte of the specified register,
rr [7:0]. The second byte
popped off the stack from (SPS+2) is written to the High byte of the specified register,
rr [15:8]. The SPS increments by 2.
Condition Bits Affected
None.
Attributes
Mnemonic Operand ADL Mode Cycle Opcode (hex)
POP rr 0/1 3/4 kk
POP.S rr 1452, kk
POP.L rr 0549, kk

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English