ZiLOG eZ80 User Manual

eZ80
®
CPU
User Manual
UM007714-0908 Memory Mode Switching
32
RETI 1 RETI
assembles to
ED 4D
The starting program counter is PC[23:0]. Pop a 3-
byte return address from SPL into PC[23:0]. The
ADL mode bit remains set to 1. The ending
program counter is PC[23:0].
RETI.S 0 — Because RETI.S is an invalid suffix, RETI.L must
be used in all mixed-memory mode applications.
RETI.L 0 RETI.LIS
assembles to
49 ED 4D
The starting program counter is {MBASE,
PC[15:0]}. Pop a byte from SPL into ADL to set
memory mode (03h = A D L , 02h = Z 8 0 ) .
if ADL mode {
Pop the upper byte of the return address from SPL
into PC[23:16].
Pop 2 LS bytes of the return address from {MBASE,
SPS} into PC[15:0].
The ending program counter is PC[23:0].
}
else Z80 mode {
Pop a 2-byte return address from {MBASE,SPS}
into PC[15:0]. The ending program counter is
{MBASE, PC[15:0]}.
}
RETI.L 1 RETI.LIL
assembles to
5B ED 4D
The starting program counter is PC[23:0]. Pop a
byte from SPL into ADL to set memory mode
(03h = ADL, 02h = Z80).
if ADL mode {
Pop a 3-byte return address from SPL into PC[23:0].
The ending program counter is PC[23:0].
}
else Z80 mode {
Pop a 2-byte return address from SPL into PC[15:0].
The ending program counter is {MBASE,
PC[15:0]}.
}
Table 19. RETI Instruction (Continued)
User Code
ADL
Mode
Assembled
Code Operation

ZiLOG eZ80 Specifications

General

Brand	ZiLOG
Model	eZ80
Category	Computer Hardware
Language	English