Abit KN9S - Page 44

DRAM Configuration:
Click <Enter> key to enter its submenu.
You may manually set the DRAM timing parameters through the following sub-items, or leave
them at their default settings according to the SPD (Serial Presence Detect) data stored in the
DRAM.
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Configuration
DRAM Timing Selectable Auto Item Help
x - DRAM Clock DDR2 533
- Bank Interleaving Enabled
- DQS Timing Training Skip DQS
- CKE Base Power Down Mode Enabled
- CKE Base Power Down By Channel
- Memclock Tri-Stating Disabled
x - TwTr Command Delay 2 Clocks
x - Trfc0 for DIMM1 75 ns
x - Trfc1 for DIMM2 75 ns
x - Trfc2 for DIMM3 75 ns
x - Trfc3 for DIMM4 75 ns
x - Write Recovery Time(Twr) 4 Clocks
x - Precharge Time(Trtp) 2 Clocks
x - Row Cycle Time(Trc) 17 Clocks
x - RAS to CAS Delay(Trcd) 4 Clocks
x - RAS to RAS Delay(Trrd) 2 Clocks
x - Row Precharge Time(Trp) 4 Clocks
x - Min. RAS Act-Time(Tras) 12 Clocks
- CAS Latency Auto
- Command Rate Auto
Memory Hole remapping Enabled
Auto Optimize Bottom IO Enabled
↓↑ →← :Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
 Back to Advanced Chipset Features Setup Menu:
SSE/SSE2 Instructions
This item allows you to Enable or Disable the SSE/SSE2 (Streaming SIMD Extensions)
instruction set.
Init Display First
This item selects which display slot to initialize first when the system boots.
System BIOS Cacheable
This item enables or disables caching the system BIOS for faster execution.
3-10 KN9 SLI, KN9 Ultra, KN9S