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Abit Vi7 - Page 48

Abit Vi7
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3-12 Chapter 3
Back to Advanced Chipset Features Setup Menu:
CPU & PCI Bus Control:
Click <Enter> key to enter its submenu:
PCI Master 0 WS Write:
Two options are available: Enabled or Disabled. The default setting is Enabled. When Enabled, writes to
the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is
set to Disabled, the system will wait one state before data is written to the PCI bus.
Vlink 8X Support:
Two options are available: Disabled or Enabled. The default setting is Enabled. This item can let you
enable the Vlink bus data transfer between northbridge and southbridge.
Back to Advanced Chipset Features Setup Menu:
Top Performance:
This item enables the DRAM performance if there are no compatible issues occurred.
VI7

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