System Management
7450 ESS OS Basic System Configuration Guide Page 245
PTP Clock Synchronization
The IEEE 1588v2 standard allows for synchronization of the frequency and time from a master
clock to one or more slave clocks over a packet stream. This packet-based synchronization can be
over UDP/IP or Ethernet and can be multicast or unicast. Only IPv4 unicast mode with unicast
negotiation is supported on the 7450 ESS
As part of the basic synchronization timing computation, a number of event messages are defined
for synchronization messaging between the PTP slave clock and PTP master clock. A one-step or
two-step synchronization operation can be used, with the two-step operation requiring a follow-up
message after each synchronization message. Currently, only one-step operation is supported on
the 7450 ESS. A 7450 ESS configured as an ordinary master clock operates in one-step mode. A
7750 SR configured as an ordinary slave clock can communicate with both one-step and two-step
master clocks.
During startup, the PTP port in selected into Slave state receives the synchronization messages
from the external peer providing the master port service. Prior to any delay calculation, the delay
is assumed to be zero. A drift compensation is activated after a number of synchronization
message intervals occur.
The basic synchronization timing computation between the PTP slave and PTP master is shown in
Figure 14. This figure illustrates the offset of the slave clock referenced to the best master signal
during startup.
Figure 12: PTP Slave and Master Time Synchronization Computation
Master Slave
Sync
Follow_up (t1)
Delay_req
Delay_resp (t4)
38
40
42
44
46
48
50
52
54
56
58
60
62
40
42
44
46
48
50
52
54
56
58
60
62
64
O = Offset = Slave - Master
t1, t2, t3, t4 Are Measured Values
t2 - t1 = Delay + Offset = 51 - 44 = 7
t4 - t3 = Delay - Offset = 57 - 56 = 1
Delay = ((t2 - t1) + (t4 - t3))/2 = 4
Offset = ((t2 - t1) - (t4 - t3))/2 = 3
D = Delay
t1
t2
t2
OD
OSSG732
t3
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