BASIC
OPERATING THEORY
COMMODORE-AMIGA
1000 SYSTEM
SLIDE 1
—
AMIGA
BLOCK
The
Amiga
1000
System
actually utilizes
two 16
Bit Bi-directional
Data
3uses
and
four
Address
Buses. The Data
Bus
connects the System
RAM to all 3
Custom
ICs
and
68000 MPU
through
Bi -Directional
Tri-State
Buffers.
DATA
BUSES
1.
One of the
Data Buses, (On
Left), is called
the
Micro
Processor,
(up)
, or
68K Data
Bus,
(PD0-PD15)
, and is used
to connect the 68000
MPU
to
the
Expansion
Bus, O/S RAM/ROM and
the 8520
CIA
Chips.
2. The other Data
Bus is
called
the Display/uP
Data
Bus,
(D0-D15) ,
and
is used
to connect the System
RAM directly
to all
three
Custom
Chips and also
too
the 63000 MPU through a
Bi-Directional
Tri-State
Buffer
when no DMA is
occuring.
ADDRESS
BUSES
1.
One
Address Bus,
(A1-A23
-
Not
Shown)
,
is a 23
Bit Bus and
is
generated
either by the 68000 MPU or
an External
Bus Master.
2. One Address
Bus is 8 Bits Multiplexed,
(RA0-RA7)
,
(Low Bits), and
is
generated
by either Agnus
or the 68000 MPU.
If this bus is
generated
by
Agnus the multplexinq is done,
(Hi to
Lo
Bit),
if it is
generated by the
63000 MPU
it
must
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(Lo
-
Hi Bits
Shown on Amiga
Block)
3. One
Address Bus is
18 Bits,
(Multiplexed to 9
-
DRA0-DRA8)
,
generated
by Agnus and is
used to
address the Dynamic RAMs
during DMA. or Refresh.
'
(Shown on
DMA
Read
arid
Agnus Block)
4. One Address Bus
is 8 Bits,
(RGA1-RGA8), generated by either Agnus or
the
68000
and
is
used for
Inner-Chip Communication.
During a
DMA Cycle,
this
Bus *
is
Bi
-Directional only
on Agnus thus allowing Agnus*' t o act
as
a Co-Processor Z
3
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£
0'£
When no
DMA is occurring
the
RGA Bus
is driven
by the
Lo Address Bits of
the
63000
MPU. This allows the
68000 MPU to Read
or Write
to
the
Custom Chips
as though they
were RAM.
(Shown
on
Agnus Block)
This
type of
design
allows
the
68000
MPU to
run without
interference
from DMA
Cycles used for
Display, Blitter
etc.
When Agnus
decides
a DMA
Cycle is required, it turns
on the Data
Bus
Request
Line, DBR, on a falling edge
of the
Color Clock,
CCK) ,
also
known as
CI.
The
Bus
Control Logic, (which contains
the 'PALEN' PAL), enables
the
DMA
Address
Enable
Signal, (DAE),
preventing
the
DTACK
Signal
which interrupts
the
68000 MPU
and
turns off both Tri-State
Buffers.
In this DMA
Mode,
AGNUS addresses RAM using its
RAM
Address
Bus, DRA,
while
simultaneously creating a Data Destination
Address
on the
Register
Address
Bus,
RGA.
This selects a Register on
any of
the
Custom
ICs, including
itself, as
the
RAM Data
Destination.
All Agnus Cycles
are
16 ^it
Transfers.
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