Amiga 1000 - Page 33

BASIC
OPERATING THEORY
COMMODORE-AMIGA
10°0 SYSTEM
The Arr.iaa
1000
System actually
utilizes
two
16
Bit Bi-directional
Data
Buses
and
four
Address 3uses.
The Data
Bus connects the System RAM to all 3
Custom
ICs
ar.i
63C00
MPU through
a Bi-Directional
Tri-State
Buffer.
DATA
BUSES
1. One
of the Data Buses is
called
the Micro Processor, (up) , or
63K
Data
Bus,
(PD0-PD15) , and is *. sed to
connect
the
68000
MPU
to
the
Expansion Bus,
O/S
RAM/ROM and
the
8520 CIA Chips.
2. The
other
Data Bus is called
the Display/uP Data
Bus, (D0-D15) ,
and
is used
to
connect the System RAM
directly to all
three Custom Chips
and also too
the 68000
MPU
through Bi-Directional
Tri-State
Buffers
when no
DMA
is
occuring.
ADDRESS BUSES
1.
One
Address
Bus,
(A1-A23)
,
is a 23 Bit
Bus
and
is generated either
by
the
63000 MPU or
an External Bus
Master.
2. One
Address Bus
is 8 Bits
Multiplexed,
(RA0-RA7)
, and is generated by
either
Agnus
or
the
68000 MPU. If this
bus is
generated by
Agnus the multplexing
is done,
(Hi
to
Lo
Bit)
,
if it is generated
by the 68000
MPU
it
must
be
multiplexed
before
RAM.
3.
One
Address
Bus
is
18
Bits,
(Multiplexed to 9
-
DRA0-DRA8), generated
by Agnus
and is
used
to
address
the
Dynamic
RAMs
during DMA or
Refresh.
4.
One Address Bus is
8
Bits, (RGA1-RGA8)
,
generated
by
either
Agnus or the
68000
and
is
used for Inner-Chip
Communication. During a DMA
Cycle,
this Bus
is Bi-Directional only on Agnus thus
allowing Agnus'
Co-Processor
control.
When
no DMA is
occurring the RGA Bus is
driven by the Lo
Address Bits of the
68000
MPU.
This
allows
the
68000
MPU
to Read
or
Write to the
Custom Chips
as
though they
were RAM.
This type
of
design allows the
68000
MPU to run
without interference
from
DMA
Cycles used
for
Display,
Blitter
etc.