Amiga 1000 - Page 34

BASIC OPERATING
THEORY
COMMODORE-AMIGA
1000 SYSTEM
There
are
two basic types of RAM
Cycles
in
the Arciga. One is called
the 63K
or
Processor
Access
and the other is cal.'.ed
the Agnus Access.
Agnus Access
When
Agnus decides
a
DMA Cycle is
required, it
turns
on DBR*,
(Data
Bus
Request),
on a
falling edge of the Color Clock,
CCK)
,
also
known
as
CI. DBR*
is
input to the PALEN
PAL,
(U5L)
,
which
enables the DAE*,
(DMA
Address
Enable),
signal. DAE
will
turn on
with the next
rising
edge of
Cl and
stay on until
the
next
falling edge
of
C3.
The DAE*
Signal will
turn on the outputs of
a
Tri-State Latch,
(U2H) , which
drives the
RAM Address Lines, (RA0-RA7)
.
At
this
time
the latch contains the
Row
Address
loaded
from Agnus
DRA Lines.
The output
of U8G
then
goes 'Low' which turns on
RAS*,
(Row Address
Select)
,
and
the
Row Address is clocked into
the
RAMs.
When
RAS* turns
on, the output
of
U9I,
(DAC)
,
goes
'High'
and
the
Column
Address,
which
is
now
on the DRA Lines
is
clocked
into
the Tri-State
Latch,
(U2H) .
The Column
Address
is
clocked directly
into the RAMs because
the outputs
of the
latch are
still
enabled by
DAE*.
The
DAE* is
also input to the PALCAS
PAL,
(05MJ ,
which
enables
the
UCEN
and
LCEN,
(Upper and
Lower
CAS
Enable), outputs.
When both
UCEN and LCEN are
on,
Cl
goes
low which
enables two Decoders, (UlH and
Ull). UCAS outputs, (U1H) , and LCAS
outputs, (Ull),
will enable
the CAS
Inputs
of the RAMs.
Agnus
Memory Read Cycle
If Agnus decides this
is to be a Read Cycle, it
will
hold
the ARW*, (Agnus
Read/Write) line 'High'. The ASK* signal is input to the PALCAS
PAL, (U5M)
,
which
keeps
the
PAL frcm generating a RRW*, (RAM Read/Write)
,
signal to
the
RAMs.
This
will cause
the RAMs
to drive the
Data Bus
and
Data
is output
frcm the RAMs.
Agnus
Memory Write Cycle
If Agnus decides this is to
be a Write Cycle, it
will
output
a
'LOW' signal on
the
ARW*,
(Agnus
Read/Write)
,
line at the beginning
of the cycle. The ARW*
signal
is input to the
PALCAS PAL, (U5M) , which will
generate a RRW*, (RAM
Read/Write)
,
signal
to
the
RAMS
before
CAS is turned on. This will cause
Agnus to
drive
the
Data
Bus
and
Data is clocked into the RAMs.
Since the
PALCAS
PAL
turns on
the RRW*
before
CAS
turns on, the RAMs can
never
turn
on their
outputs. This is necessary when using 64K x 4 RAMs.
When Cl goes 'High'
again, the cycle is
complete
and
Agnus is
ready
for
a
new
cycle
to
begin.