Amiga 1000 - Page 35

BASIC OPERATING
THEORY
COMMODORE-AMIGA
1000
SYSTEM
68K
Access
When
the 68000 MPU
decides
to do a
Read
Cycle,
it turns on
the AS*,
(Address
Strobe)
,
output to the PALEN
PAL, (U5L) .
When
the
address is in
the
right
range
for
the RAMs and Cl is
'High' and
C3
is 'Law', the
PAL
turns on
the
RE*,
(RAM
Enable),
signal. This
RE* signal
enables
two
multiplexers,
(U2I
and U2J)
. These
multiplexers drive
Al thru A8
into the
RAM
Array.
The
RAS*, (Row
Address
Select),
output
from U8G to
the RAMs then
goes 'Low' which
clocks
the
Row Address.
The RE* signal
is
also
input to
the PALCAS
PAL.
Since
this
is
a
Read
Cycle,
the PAL
generates a CDR*, (CPU Data
Read)
,
signal and
also the
UCEN, (Upper CAS
Enable),
and/or
the LCEN,
Lower
CAS
Enable).
The CDR* signal
from
the PAL turns on
the
outputs
of
two latches,
(U3H
and
U3J)
,
which
catch the Data
caning
out
of the
RAMs. Since
the RAM
Cycle ends
before
the 68C00 MPU's Bus
Cycle
is
over,
the latches must
hold
this
data.
UCEN turns on only
if
UDS*, (Upper Data Strobe)
,
from
the
68000
is also on and
LCEN turns on only if LDS*,
(Lower
Data Strobe),
from the 68000 is on. This
is
done to generate separate
CAS
signals
for
doing
Byte Writes.
When
Cl goes
low,
whichever
CAS is enabled
will turn on causing
the
RAMs
to
output Data on the Data Bus. Because the
CDR* Signal from
the
PAL
is still
keeping the outputs of the
latches on,
the Data coming
from the
RAMs
is
caught
and
latched. With Cl still
'Low',
C4 .goes 'Low' which
shuts the latches
and
saves
the RAM
Data. The RAM Data is
then driven
onto
the 68000
Bus.
This Data
will stay on the Bus. until the 68000
releases
both
UDS*
and
LDS*,
at
which time CDR* is
no longer active.