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ADE9000 Technical Reference Manual UG-1098

Rev. 0 | Page 43 of 86

INTERRUPTS/

EVENT

The ADE9000 has three pins,

IRQ0

IRQ1

, and CF4/

EVENT

DREADY, which can be used as interrupts to the host processor.

The

IRQ0

and

IRQ1

pins go low when an enabled interrupt

occurs and stay low until the event is acknowledged by setting

the corresponding status bit in the STATUS0 and STATUS1

registers, respectively. The

EVENT

function, which is

multiplexed with the CF4 and DREADY options on the

CF4/

EVENT

/DREADY pin, tracks the state of the enabled

signals and goes low and high with these internal signals. The

EVENT

function is useful for measuring the duration of events,

such as dips or swells, externally.

INTERRUPTS (

IRQ0

AND

IRQ1

)

The

IRQ0

and

IRQ1

pins are managed by 32-bit interrupt mask

registers, MASK0 and MASK1, respectively. Every event that

can generate an interrupt has a corresponding bit in the MASK0

or MASK1 register and the STATUS0 or STATUS1 register.

To enable an interrupt, set the corresponding bit in the

MASK0 or MASK1 register to 1. To disable an interrupt, the

corresponding bit in the MASK0 or MASK1 register must be

cleared to 0.

The STATUS0 and STATUS1 registers indicate if an event that

can generate an interrupt has occurred. If the corresponding bit

in the MASK0 or MASK1 register is set, an interrupt is generated

on the corresponding

IRQ0

IRQ1

pin, and the pin goes low.

To determine the source of the interrupt, read the

corresponding STATUS0 or STATUS1 register and identify

which enabled bits are set to 1. To acknowledge the event and

clear bits in the STATUSx register, write to the STATUSx

corresponding

IRQ0

IRQ1

pin goes high.

For example, if a zero-crossing occurs on the Phase A voltage

input and the ZXVA bit is set in the MASK1 register, the

IRQ1

pin goes low, indicating that an enabled event has occurred. To

acknowledge the event, write a 1 to the ZXVA bit in the

STATUS1 register, and then the

IRQ1

pin goes low. The ZXVA

STATUS1 bit is set regardless of whether the ZXVA bit is

enabled in MASK1.

There are a few interrupts that are nonmaskable, meaning that

they are generated even if the corresponding bit in the MASKx

and ERROR0.

There is an option to combine all the interrupts onto a single

interrupt pin,

IRQ1

, instead of using two pins,

IRQ0

and

IRQ1

To activate this option, set the IRQ0_ON_IRQ1 bit in the

CONFIG1 register. Note that the

IRQ0

pin still indicates the

enabled

IRQ0

events while in this mode, and

IRQ1

indicates

both

IRQ1

and

IRQ0

events.

The meaning of each individual interrupt source is provided in

the related data sheet section; refer to these sections in the

ADE9000 data sheet for more information.

EVENT

The

EVENT

function is multiplexed with CF4 and DREADY on

the CF4/

EVENT

/DREADY pin. To enable the

EVENT

function

to be output on this pin, write CF4_CFG = 10 in the CONFIG1

There are 16 signals that can be incorporated into the

EVENT

pin and are selected in the EVENT_MASK register. All of these

events sources are maskable and disabled by default.

The logic level of the

EVENT

output is solely dependent on the

enabled events; it cannot be changed by the user. If any of the 16

events are enabled by setting their corresponding mask bit to 1

in the EVENT_MASK register, the

EVENT

pin goes low

whenever one of the enabled events occurs and stays low until

all the enabled signals have gone high. Then, the

EVENT

goes high. Note that the status sources used to generate the

EVENT

are not latched; if one event source is selected, the

EVENT

pin tracks the status of that source.

STATUS BITS IN ADDITIONAL REGISTERS

Several interrupts are used in conjunction with other status

registers.

Overcurrent

The OI bit in the MASK1 register works in conjunction with the

OIPHASE status bits in the OISTATUS register.

No Load

The VAFNOLOAD, RFNOLOAD, AFNOLOAD, VANLOAD,

RNLOAD, and ANLOAD bits in the MASK1 register work in

conjunction with additional status bits in the PHNOLOAD register.

The following bits in the MASK0 register work with the status

bits in the PHSIGN register: REVAPx, REVRPx, and REVPSUMx.

Read the additional registers to obtain more information when

the corresponding bits are set in the STATUSx register.

Brand	Analog Devices
Model	ADE9000
Category	Measuring Instruments
Language	English

Analog Devices ADE9000 User Manual

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