Apache Labs ANAN-100/D - Appendix - G the CORDIC Algorithm

Apache Labs ANAN-100/D
Appendix – G The CORDIC Algorithm
The CORDIC mathematical algorithm used in the Apache-100W Transceiver;
CORDIC - Wikipedia, the free encyclopedia
http://en.wikipedia.org/wiki/CORDIC
CORDIC FAQ
http://www.dspguru.com/dsp/faqs/cordic
CORDIC FAQ-II
http://www.dspguru.com/info/faqs/cordic2.htm
CORDIC for Dummies
http://www.jacques-laporte.org/cordic_for_dummies.htm
The CORDIC Algorithm
http://www.andraka.com/cordic.htm
CORDIC
http://www.nist.gov/dads/HTML/cordic.html
From Hermes VHDL designer Phil Harman VK6APH:
The CORDIC takes the input samples and multiplies them by the sine and cosine of the phase value we
feed to it (i.e. the frequency we want to tune to). The CORDIC is a successive approximation approach to
generating the sine and cosine of an angle - since it only uses add and shift logic it was used in the early hand-
held calculators. If we use enough bits in the CORDIC then the sine and cosine values it generates are so
accurate that we get perfect I & Q signals out in terms of how well the amplitudes are matched and how close
to 90 degrees apart they are.
As I said it is a successive approximation approach so it takes about 20 iterations to get the accuracy we
need. In which case there is a delay of 20/122.88MHz from the time the RF appears at its input to the time the I
and Q signals appear.
Because of this delay we use a technique called pipelining - we feed samples into a pipe that is 20
samples long and at the end of the pipe take the result out.
We decimate and filter at the same time. The CIC is a very simple way to produce a filter (just adds and
subtracts) so it is very efficient to implement in the FPGA. But it's frequency response is not ideal so we follow it
with a CFIR that compensates for the droop in the CIC passband and cleans up the overall shape.
The Hermes FPGA Verilog code can be found on the SVN http://openhpsdr.org/download.php
Revision v1.8 April 23, 2013 55 of 70 authors N9VV and KC9XG