Atari Super Breakout User Manual

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erates an

enable

signal

that

allows

the

shift

register

serial data

previously

loaded

into

it

from

the

motion

object

video

RO

Ms

to

be

shifted

out.

The serial

video

information

for

each

of

the

motion

objects

is

then

summed

into

the

video

summing

circuit

(as

shown

on

sheet 4

of

the

schematic diagram).

G.

SWITCH

INPUT

CIRCUITRY

(See

Figure

3-3,

Sheet

•

of

5)

All

off-board

control

switch

inputs

as

well

as

on-

board

DIP switch

inputs

are received and

decoded

by

data

selector

MB.

All

switch

inputs

are

multiplexed

down

to

two

input

lines (pins 7 and 9

of

M8) via H9,

J9,

and

MPU

address lines

AORO-AOR2.

These

two

lines

(pin

7 and 9

of

MB

are

then

gated

onto

the

MPU

data

bus

(06-07)

by

the

MPU

address

decode

SWITCH.

When

the

MPU

wants

to

look

at any

switch,

it

merely

addresses

that

switch

and reads back its

status

on

either

06

or

07.

See

MPU

memory

map

address

output

and

corresponding

data

input

line

for

any

of

the

game's switches.

D.

PADDLE

CONTROL

(See

Figure

3-3,

Sheet

2

of

5)

The

paddle

control

is

a

linear

clutched

poten-

tiometer

(POT)

with

one

side

of

the

resistive

element

VOLTAGE

RAMP

DC

VOLTAGE FROM

+12V

WIPER OF POT (L 10, PIN 10)

I

I

I I

I :

I I

to

ground,

and

the

other

side

to

+5

volts. The

wiper

of

the

pot

is

then

connected

to

the

inverting

input

of

comparator

device L 10,

pin

10.

A ramp

generator

comprised

of

transistors

Q1,

Q2, and

Q6

and

capacitor

C53

produces

a

positive-

going

ramp

with

a slope

determined

by

capacitor

C53. This ramp is

inhibited

at each VBLANK

pulse

which

occurs

on

each

picture

frame. VBLANK

turns

Q1

"on",

which

created a

direct

short

across C53,

discharging

the

voltage across

it

as

illustrated

in Fig-

ure

3-14.

When

VBLANK goes

low

Q1

turns

"off",

removing

the

short

from

across

C53

and

allowing

it

to

begin

charging

up

through

Q2.

Voltage

follower

Q6

buffers

the

positive

ramp

to

the

non-inverting

input

of

comparator

L 10,

pin

9.

As

the

player rotates

the

paddle

knob,

the

wiper

voltage

will

at

times

match

or

cross

the

ramp voltage and

the

output

of

L 10,

pin

7,

will

go

high.

This occurs each and

every

time

these

two

voltages cross.

This

high

comparator

output

is gated

to

the

SENSE

1

line

when

the

MASK 1 signal is

low

and

enables

the

M10,

pin

8, gate. MASK 2

is

always

low,

inhibiting

gate M10,

pin

11, because

there

is

only

one

paddle

available

to

the

player

for

the

Super Breakout

This

time

difference

indicates

to

the

MPU

program

what

the

vertical

location

of

the

paddle

should

be.

APPROXIMATE COMPARATOR

LIMITS WIPER

VOLTAGE

~~',,

n~n~~n~~n~~~

'V'

I

\.

~

' A PICTURE

Q1

OFF

~

FRAME

Q1

ON (SHORT ACROSS CAPACITOR)

Figure

3-14

Significant Paddle Signals

and

Timing

3 ·14 Super Breakout

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Atari Super Breakout Specifications

General

Brand	Atari
Model	Super Breakout
Category	Video Gaming Accessories
Language	English