ATtiny15L
33
EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 1.1 - 2.1 ms, depending on the V
CC
voltages. A self-timing function, however, lets
the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some
precautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly on power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used.
CPU operation under these conditions is likely to cause the program counter to perform unintentional jumps and eventually
execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset
circuit in this case.
In order to prevent unintentional EEPROM writes, a two-state write procedure must be followed. Refer to the description of
the EEPROM Control Register for details on this.
When the EEPROM is read or written, the CPU is halted for two clock cycles before the next instruction is executed.
The EEPROM Address Register – EEAR
•
Bit 7,6 - Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and will always read as zero.
•
Bit 5..0 - EEAR5.0: EEPROM Address
The EEPROM Address Register – EEAR specifies the EEPROM address in the 64 bytes EEPROM space. The EEPROM
data bytes are addresses linearly between 0 and 63. The initial value of EEAR is undefined. A proper value must be written
before the EEPROM may be accessed.
Table 15. Watch Dog Timer Prescale Select
WDP2 WDP1 WDP0 Time-out Period
0 0 0 16K cycles
0 0 1 32K cycles
0 1 0 64K cycles
0 1 1 128K cycles
1 0 0 256K cycles
1 0 1 512K cycles
1 1 0 1024K cycles
1 1 1 2048K cycles
Bit 7 6 5 4 3 2 1 0
$1E - - EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEAR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial value 0 0 X X X X X X
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