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ATtiny15L
1187H–AVR–09/07
• Bits 3, 2, 1, 0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.
The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes
are scaled directly from the CK oscillator clock.
The Timer/Counter1 – TCNT1
This 8-bit register contains the value of Timer/Counter1.
Timer/Counter1 is implemented as an up-counter with read and write access. Due to
synchronization of the CPU and Timer/Counter1, data written into Timer/Counter1 is
delayed by one CPU clock cycle.
Table 11. Timer/Counter1 Prescale Select
CS13 CS12 CS11 CS10 Description
0000Timer/Counter1 is stopped.
0001CK*16 (=PCK)
0010CK*8 (=PCK/2)
0011CK*4 (=PCK/4)
0100CK*2 (=PCK/8)
0101CK
0110CK/2
0111CK/4
1000CK/8
1001CK/16
1010CK/32
1011CK/64
1100CK/128
1101CK/256
1110CK/512
1111CK/1024
Bit 76543210
$2F MSB LSB TCNT1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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