13
8068C–AVR–06/08
XMEGA A3
7.7 Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory is organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 13 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at the time, while reading the Flash is done one byte at
the time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant
bits in the address (FPAGE) gives the page number and the least significant address bits
(FWORD) gives the word in the page.
Table 7-2. Number of words and Pages in the Flash.
Table 7-3 on page 13 shows EEPROM memory organization for the XMEGA A3 devices.
EEEPROM write and erase operations can be performed one page or one byte at the time, while
reading the EEPROM is done one byte at the time. For EEPROM access the NVM Address
Register (ADDR[m:n] is used for addressing. The most significant bits in the address (E2PAGE)
gives the page number and the least significant address bits (E2BYTE) gives the byte in the
page.
Table 7-3. Number of bytes and Pages in the EEPROM.
Devices Flash Page Size FWORD FPAGE Application Boot
Size (Bytes) (words) Size No of Pages Size No of Pages
ATxmega64A3 64K + 4K 128 Z[7:1] Z[16:8] 64K 256 4K 16
ATxmega128A3 128K + 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16
ATxmega192A3 192K + 8K 256 Z[8:1] Z[18:9] 192K 384 8K 16
ATxmega256A3 256K + 8K 256 Z[8:1] Z[18:9] 256K 512 8K 16
Devices EEPROM Page Size E2BYTE E2PAGE No of Pages
Size (Bytes) (Bytes)
ATxmega64A3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega128A3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega192A3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega256A3 4K 32 ADDR[4:0] ADDR[11:5] 128
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