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8068C–AVR–06/08

XMEGA A3

13. PMIC - Programmable Multi-level Interrupt Controller

13.1 Features

• Separate interrupt vector for each interrupt

• Short, predictable interrupt response time

• Programmable Multi-level Interrupt Controller

– 3 programmable interrupt levels

– Selectable priority scheme within low level interrupts (round-robin or fixed)

– Non-Maskable Interrupts (NMI)

• Interrupt vectors can be moved to the start of the Boot Section

13.2 Overview

XMEGA A3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can

define three different priority levels for interrupts; high, medium or low. Medium level interrupts

may interrupt low level interrupt service routines. High level interrupts may interrupt both low-

and medium level interrupt service routines. Low level interrupts have an optional round robin

scheme to make sure all interrupts are serviced within a certain amount of time.

The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).

13.3 Interrupt vectors

When an interrupt is serviced, the program counter will jump to the interrupt vector address. The

interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for

specific interrupts in each peripheral. The base addresses for the XMEGA A3 devices are shown

in Table 13-1. Offset addresses for each interrupt available in the peripheral are described for

each peripheral in the XMEGA A manual. For peripherals or modules that have only one inter-

rupt, the interrupt vector is shown in Table 13-1. The program address is the word address.

Table 13-1. Reset and Interrupt Vectors

Program Address

(Base Address) Source Interrupt Description

0x000 RESET

0x002 OSCF_INT_vect Crystal Oscillator Failure Interrupt vector (NMI)

0x004 PORTC_INT_base Port C Interrupt base

0x008 PORTR_INT_base Port R Interrupt base

0x00C DMAC_INT_base DMA Controller Interrupt base

0x014 RTC_INT_base Real Time Counter Interrupt base

0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base

0x01C TIMERC0_INT_base Timer/Counter 0 on port C Interrupt base

0x028 TIMERC1_INT_base Timer/Counter 1 on port C Interrupt base

0x030 SPIC_INT_vect SPI on port C Interrupt vector

0x032 USARTC0_INT_base USART 0 on port C Interrupt base

0x03D USARTC1_INT_base USART 1 on port C Interrupt base

0x03E AES_INT_vect AES Interrupt vector

Atmel XMEGA A3 series User Manual

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