Camera Link Implementation AW00118702000
12 Basler racer Camera Link
1.5 Camera Link Output Signals
1.5.1 Serial to Frame Grabber
The Serial To Camera (SerTFG) input signal is an RS-644 LVDS signal as specified in the Camera
Link standard. The signal is output from the camera on pins 8 and 21 of the base SDR connector
as specified in the standard and as shown in Fig. 2 on page 6. The camera is equipped for RS-644
serial communication via a serial port integrated into the frame grabber as specified in the Camera
Link standard.
The RS-644 serial connection in the Camera Link interface is used to issue commands to the
camera that change parameter values. The serial link can also be used to query the camera about
its current setup.
1.5.2 Pixel Clock
The pixel clock is used to time the sampling and transmission of pixel data. The frequency of the
pixel clock (pixel clock speed) is selectable.
For more detailed information about the pixel clock speed, see Section 2 on page 25.
The pixel clock is assigned as defined in the Camera Link standard to the strobe ports (TxClk pins)
of the following transmitter circuits:
transmitter circuit X as shown in Table 2 and in Fig. 2, Fig. 3, Fig. 4, Fig. 5, and Fig. 6.
transmitter circuit Y as shown in Table 3 and in Fig. 3, Fig. 4, Fig. 5, and Fig. 6.
transmitter circuit Z as shown in Table 3 and in Fig. 4, Fig. 5, and Fig. 6.
1.5.3 Line Valid Bit
As shown for example in Fig. 10 on page 31, the line valid bit indicates that a valid line is being
transmitted. Pixel data is only valid when the line valid bit and the data valid bit are both high.
(In those cases where the data valid bit is not available (see Section 1.5.4 on page 13), pixel data
is valid when the line valid bit is high.)
The line valid bit is assigned as defined in the Camera Link standard to the line valid ports of the
following transmitter circuits:
transmitter circuit X as shown in Fig. 2, Fig. 3, Fig. 4, Fig. 5, and Fig. 6.
transmitter circuit Y as shown in Fig. 3, Fig. 4, Fig. 5, and Fig. 6.
transmitter circuit Z as shown in Fig. 4, Fig. 5, and Fig. 6.
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