Camera Link Implementation AW00118702000
18 Basler racer Camera Link
1.5.6.4 1X8 Tap Geometry – 8 or 10 Bit Pixel Depth
* In 1X8 8 bit mode, this port is DVAL.
In 1X8 10 bit mode, DVAL is not present. Instead, this port is I0 and D0 Bit 0 is assigned to it.
Base SDR Conn, Transmitter Circuit X
Port Camera Frame
Grabber
Bit Assignments
1X8 - 8 Bits 1X8 - 10 Bits
Port A0 TxIn0 RxOut0 D0 Bit 0 D0 Bit 2
Port A1 TxIn1 RxOut1 D0 Bit 1 D0 Bit 3
Port A2 TxIn2 RxOut2 D0 Bit 2 D0 Bit 4
Port A3 TxIn3 RxOut3 D0 Bit 3 D0 Bit 5
Port A4 TxIn4 RxOut4 D0 Bit 4 D0 Bit 6
Port A5 TxIn6 RxOut6 D0 Bit 5 D0 Bit 7
Port A6 TxIn27 RxOut27 D0 Bit 6 D0 Bit 8
Port A7 TxIn5 RxOut5 D0 Bit 7 (MSB) D0 Bit 9 (MSB)
Port B0 TxIn7 RxOut7 D1 Bit 0 D1 Bit 2
Port B1 TxIn8 RxOut8 D1 Bit 1 D1 Bit 3
Port B2 TxIn9 RxOut9 D1 Bit 2 D1 Bit 4
Port B3 TxIn12 RxOut12 D1 Bit 3 D1 Bit 5
Port B4 TxIn13 RxOut13 D1 Bit 4 D1 Bit 6
Port B5 TxIn14 RxOut14 D1 Bit 5 D1 Bit 7
Port B6 TxIn10 RxOut10 D1 Bit 6 D1 Bit 8
Port B7 TxIn11 RxOut11 D1 Bit 7 (MSB) D1 Bit 9 (MSB)
Port C0 TxIn15 RxOut15 D2 Bit 0 D2 Bit 2
Port C1 TxIn18 RxOut18 D2 Bit 1 D2 Bit 3
Port C2 TxIn19 RxOut19 D2 Bit 2 D2 Bit 4
Port C3 TxIn20 RxOut20 D2 Bit 3 D2 Bit 5
Port C4 TxIn21 RxOut21 D2 Bit 4 D2 Bit 6
Port C5 TxIn22 RxOut22 D2 Bit 5 D2 Bit 7
Port C6 TxIn16 RxOut16 D2 Bit 6 D2 Bit 8
Port C7 TxIn17 RxOut17 D2 Bit 7 (MSB) D2 Bit 9 (MSB)
LVAL TxIn24 RxOut24 Line Valid Line Valid
FVAL TxIn25 RxOut25 Not Used Not Used
DVAL or
Port I0 *
TxIn26 RxOut26 Not used
D0 Bit 0
Port I1 TxIn23 RxOut23 Not Used D0 Bit 1
Strobe TxInCLK RxOutClk Pixel Clock Pixel Clock
Table 8: Bit Assignments for 1X8 Tap Geometry – 8 or 10 Bit Pixel Depth (Transmitter Circuit X)