Theory of Operation Section 4
4-7
4-31. A12 Display And A13 Keyboard Circuits. The
display and keyboard circuits provide the operator inter-
face to the Model 1121A circuits. Key closures are
detected and sent to the microprocessor which interprets
and modifies the display LEDs appropriately. The
software configurable display/keyboard CPLD, U1 is
programmed to operate 16 display digits. All of the seven
segment displays are connected to a common cathode
driver bus which is generated by U1 and buffered through
U7 and current limiting resistors R118 through R125. The
LED anodes are individually connected to a buffers U3
and U4. All segment decoding is done by the CPLD so
that no additional decoders are required.
4-32. All of the alphanumeric annunciators are static and
latched by the CPLD U1. Resistors R126 through R148
limit the current through the LEDs.
4-33. The key LEDs are all static and latched by the
CPLD U1.
4-34. Keyswitch decoding is accomplished by scanning
the keyboard and detecting key closures. CPLD U1
controls the scanning of the keyboard through decoder
U17 which generates the column strobes RL0 through
RL7. Any key closure will convey the column strobe to
one of eight row lines, RR0 through RR7, which are moni-
tored by U1. Multiple key closures and key debouncing
are handled by U1. When a keyswitch closure occurs a
microprocessor interrupt is generated and processed as
described in the CPU board section.
4-35. A4 Frequency Counter Circuits. The counter
circuits provide the frequency measurement functions of
the Model 1121A. Additionally, the analog-to-digital con-
verter (A/D), the sweep output circuits, and the option
switch are located on the counter plug-in board. Refer to
Figure 4-4.
4-36. The 10 MHz internal frequency reference from the
CPU board is connected to gate U3d. The other input of
U3d is a signal derived from the external reference input.
If an external reference signal is present, pin 6 of U2a will
be a TTL compatible signal at the external reference
frequency rate. The signal is inverted by U2b and
detected by CR3, C25 and R4. When a signal is present
the input of inverter U2c will be a TTL low level which is
the control to automatically switch to the external refer-
ence using U2d, U3a, U3b, and U3d. The output of U3b
(TP2) is the reference frequency for the counter circuits
derived from either the internal or external source. DS2
will be illuminated when the external reference is active.
4-37. The analyzer frequency line ANFRQ is generated
on the detector plug-in board and is applied to hysteresis
amplifier U1a and associated components. U1a acts as a
buffer between the analog and digital sections of the
instrument and is insensitive to the noise which is present
between the analog and digital grounds. The output of
U1a (TP1) is applied to the input multiplexer, U5, of the
counter. U5 selects one of four inputs; source frequency,
analyzer frequency, external reference, and internal
reference, based on the state of control lines S0 and S1.
The output of U5 (TP4) is applied to a chain of dual
decade dividers, U6, U7 and U8. These dividers are used
for period selections and divide the selected input by
factors of 1 to 1000000 in decade increments. All the
divider output are presented to a second multiplexer, U9,
which selects one of the six period divisions based on
control lines T0, T1 and T2.
4-38. Dual flip-flop, U10, controls the arm and gate
intervals. The output of U9 (TP6) is inverted by U4b and
applied to the clock input of U10a. The arm interval
synchronizes the counter circuits to begin the gate inter-
val on the next rising edge of the measurement signal.
The ARM line is set low to clear flip-flop U10a and, after
being inverted by U4c, is applied to the master set (MS)
lines of U6, U7 and U8. The MS sets all the divider output
high which prepares the dividers to all start at count 0 with
the next falling edge of the measurement signal. The
rising edge of the ARM line clocks U10b, sets the U10b
pin 9 high and illuminates DS4. When the falling edge of
the measurement signal occurs, U10a is clocked and the
gate interval begins when U10a pin 5 goes high.
Simultaneously U10a pin 6 goes low which illuminates
DS3 and clears the arm latch U10b. When U10b is
cleared, DS4 is extinguished and U10b pin 9 is set low.
The gate interval continues until U10a pin 5 is clocked low
by the next rising edge of U10a pin 3. Gate U4a detects
the end of the arm and gate intervals and indicates to the
CPU that the count is complete. The
counter will hold the count until the next arm interval is
initiated. The output of U10a pin 5 goes to gate U3c which
allows the reference to pass to the counter accumulator
during the gate interval (TP3).
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