Section 4 Theory of Operation
4-10
waveform. Capacitor C7 is required by U6 for filter
averaging. The output of U6 (TP5) is measured by one
channel of the A/D converter on the counter plug-in
board. The signal level is measured at this stage in the
analyzer circuits for distortion and SINAD measurement
calculation and for autoranging the input attenuators and
amplifiers.
4-54. Analog switches U7a, b, and d and buffer U8 are
used to bypass or select one of two optional filter modules
when installed (TP6). Filter selection data from the CPU
circuits is latched in U3 and decoded by U4.
4-55. A2 Notch Filter Circuits. The notch filter is an
automatically tuned and balanced state-variable notch
filter. The filter is inserted into the signal path to remove
the fundamental frequency component and pass
harmonics and noise for the distortion and SINAD
measurement modes. Refer to Figure 4-7.
4-56. The notch filter consists of a state-variable
band-pass filter and a balance amplifier, U3a. In
operation the band-pass filter is tuned to the fundamental
frequency measured by the counter circuits. The output of
the band-pass filter (TP3) is then subtracted from the in-
put signal (TP1), leaving only the harmonic and noise
components of the input signal (TP9). Fine adjustment of
the notch center frequency and the amplitude of the
band-pass output is accomplished by two control loops
which operate to reduce the in-phase and quadrature
components of the fundamental signal at the output of the
balance amplifier.
4-57. The individual integrators int he filter are identical,
so only one will be described in detail. The output from
summing amplifier U1a is applied to a series of eight
resistors. The values of these resistors, R6 through R13,
are chosen in a binary series to operate as a discrete 8 bit
D/A converter. These resistors are selected for frequency
tuning within a selected frequency band by FET switches
Q1 through Q8. Capacitors C3 through C7 are selected
by FET switches 09 through Q12 for integrator tuning
over five frequency bands. Integrating amplifier U3b
completes the integrator (TP2). Coarse tuning of the filter
is provided by the selection of resistor and capacitor
combinations by the control program. Data from the
control program is latched in data latches U4 and U5. The
12 comparators contained in U6, U7, and U8 and
associated pull-up resistors R29 and R30 act as level
translators to convey the latched TTL data to gate drive
levels necessary to operate the FET switches.
4-58. The band-pass filter output is generated at the
output of inverting amplifier U2a (TP3). Balance amplifier
U3a subtracts the band-pass output from the filter input
signal forming a notch filter response. The output of the
balance amplifier is further amplified with a gain of 10 by
U10 and associated circuits. Analog switch U11a and b in
conjunction with buffer U12a select the gain depending
on range information from the control program. The
output of U12a (TP10) is further processed by the
detector circuits and used in the distortion and SINAD
measurement modes.
4-59. The balance and tuning of the filter is controlled by
synchronously detecting and reducing the in-phase and
quadrature components of the fundamental at the output
of U12a. Comparators U13a and b detect the in-phase
(TP2) and quadrature (TP5) signals in the band-pass filter
and generate gate switching levels for chopper FETs Q25
and Q26. Amplifier U12b inverts the output of U12a and
provides an out-of-phase signal to be used in generating
full-wave rectified signals for the tune and balance
integrators. The rectifier operates as follows: During the
time that switches Q25 and Q26 are shorted to ground a
current flow in resistors R48 and R49 to the integrators.
When Q25 and Q26 are open, twice as much current at
the opposite phase flows thorugh resistors R42, R47
(TP6), R43, and R50 (TP8). Since the currents are out of
phase the net current flow is the same and in the same
direction providing a full-wave rectified current to the
integrators. Integrating amplifiers U14 and U16 generate
error voltages in proportion to any in-phase or quadrature
error currents. The integrator time constants are selected
by analog switch U15 and capacitors C27 thorugh C30 to
allow optimum tracking dynamics across the tuning range
of the filter. The tune and balance error voltages are
applied to four-quadrant multipliers U17 and U18. The
current outputs through pin 4 of each multiplier is
summed together and amplified by U1b. The output of
U1b is the product of the tune and balance error voltages
and the in-phase and quadrature signals which are
summed back into the filter thorugh U1a to cancel tuning
and balance errors. The control loops can be disabled to
aid in troubleshooting the notch filter circuits by removing
jumper J1.
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