Bose CD-20 - Page 59

59
CD MECHANISM IC BLOCK DIAGRAMS
CONTROL
BLOCK
THERMAL SHUT DOWN
CONTROL
BLOCK
H
H
Vcc
Vs2
Vs1
IN1
IN2
IN3
IN4
OUT3
OUT4
OUT1
OUT2
10U
Vcont
GND
IC 862/863 (LB1836M)
PT100/P20
Port 2
Port 3
Port 0
Port 1
Bit SEQ.
Buffer:16
Basic
Interval
Timer
Timer/Event
Counter
=0
Timer/Event
Counter
=1
Serial
Interface
Programmable
Threshold
Port = 0
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 12
Port 13
Port 14
Interrupt
Control
Program
Counter
ALC
CY
SP (8)
Rom
Program
Memory
4k-16k Bytes
Decode
and
Control
Bank
General Reg.
Ram
Data Memory
320/512 X 4 Bits
Clock
Output
Control
Clock
Divider
Clock
Generator
Stand By
Control
CPC Clock
Vdd
Vss
Reset
____
F X/ 2
PCL/P22
X1
X2
T10
T11
PT01/P21
S1/PO3
SO/PO2
SCK/PO1
_______
INTO/P10
INT1/P11
INT2/P12
INT3/P13
INT4/P00
PT1100-PT1103
INTBT
INTTO
INTT1
INTS10
4
4
4
4
4
4
4
4
4
4
4
4
4
P00-P03
P10-P13
P20-P23
P30-P33
P40-P43
P50-P53
P60-P63
P70-P73
P80-P83
P90-P93
P120-P123
P130-P133
P140-P143
IC 601 (uPD75118GF-K12) Microprocessor