ICS-2003 INTERCOM STATION
3-4
TECHNICAL REFERENCE
Figure 10: Digital Block Diagram—ICS-2003 Main PCB
ICS-2003 DIGITAL BLOCK DIAGRAM
Jan. 14, 1998
PROGRAM
MEMORY
LO BYTE
PROGRAM
MEMORY
HI BYTE
RAM
MEMORY
LO BYTE
RAM
MEMORY
HI BYTE
DISPLAY CONTROLLER
DISPLAY
MEMORY
LO BYTE
DISPLAY
MEMORY
HI BYTE
ADDRESS BUS A1-A19
DATA BUS D0-D15
128K X 8 128K X 8 128K X 8 128K X 8
32K X 8 32K X 8
CE0
CE1
ADDRESS
DECODE
CE2
DISPLAY
COM
MODULE
CE3
CONTROL BUS
RXD1
TXD1
CLOCK
OSC
RESET
MICRO-PROCESSOR
ACCESSORY
PANELS
PB8
PB9
PB10
PB11
PA0
PA1
SERIAL
TEST
PORT
RXD2
TXD2
XPDOUT
XPDIN
XPDCLK
XPDSTRB
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA12
SPRXD
SPTXD
SPCLK
PB3
PB5
PB6
PB7
TIN1
TOUT2
TEST
FRNTPNL
AUDIOLEV1
AUDIOLEV2
AUDIOCNTRL
TINSEL0
TINSEL1
ADAC &
DATA
SELECT
FRONT
PANEL
POTS
TIN1
TINSEL0
TINSEL1
SPRXD
SPTXD
SPCLK
FRNTPNL
FRONT PANEL
SWITCHES AND
LEDS
DIGITALLY
CONTROLLED
POTS
SPTXD
SPCLK
AUDIOLEV2
DIGITALLY
CONTROLLED
POTS
SPCLK
SPTXD
AUDIOLEV1
ANNOUNCE
TONE
FILTER
ANNOUNCE
TONE
OUTPUT TO
AUDIO
AP TEST
PORT
SPRXD
SPTXD
SPCLK
TEST
SPI SERIAL DATA BUS
ADAC CONTROL
DTMF
GENERATOR
SPI 8 BIT
SHIFT
OUT REG
SPI 8 BIT
SHIFT
IN REG
MUTE RELAY
AUX RELAY
TALK ENABLE
SA ENABLE
LOGIC IN 1
LOGIC IN 2
HEAD SENSE
SPI 8 BIT
SHIFT
OUT REG
INTERNAL IN/OUT CONTROL REGISTERS UNDER SPI CONTROL
SPITXD
SPICLK
AUDIOCNTRL
SPICLK
AUDIOCNTRL
SPICLK
AUDIOCNTRL
SPIRXD
AUDIOLEV3
FPSTRB
DIGITALLY
CONTROLLED
POTS
SPTXD
SPCLK
AUDIOLEV3
SPK SPK
EAR 1 EAR 1
EAR 2 EAR 2
INTERCOM VOLUME PROGRAM VOLUME MISC. CONTROLS
PANEL
MIC
HEAD MIC
SIDE
EAR 1
SIDE
EAR 2