5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LAYOUT NOTE:
PLACE NEAR CPU
H_TDO,H_TDI,H_TMS
WITHIN 1.5" OF PCH PIN (PU)
CAD Note: Capacitor need to be placed
close to buffer output pin
100 MHz
100 MHz
24 MHz
Coffee Lake-S Processor 2/6 (JTAG,CLK,CFG )
H_TCK TERMINATION PLACE NEAR CPU
WITHIN 1.1 INCH (PD)
DESIGN NOTE:
DESIGN NOTE:
CFG[4]
1:Disabled - No Physical Display Port
attached to Embedded DisplayPort*.
No connect for disable.
0:Enabled - A Display Port device is
connected to the Embedded Display Port.
Pull-down to GND through a 1 K? ±5%
resistor to enable port.
DESIGN NOTE:
CFG[6:5]
00 = 1x8, 2x4 PCI Express* 01 = reserved
10 = 2x8 PCI Express* 11 = 1x16 PCI Express*
Recommend 1K ? ±5% pull-down resistor to GND.
PU/PD for JTAG signals
DESIGN NOTE:
CFG[7]
1 = (default) PEG train immediately following
RESET# de assertion.
0 = PEG wait BIOS for training.
modify,0514 max
modify,0526 max
㍉岤modify,0703 max
CFG1
CFG3
CFG8
DDR_VTT_CTRL
DDR_VTT_CTRL
SKL_CNL#
H_CATERR#
H_PROCHOT#
H_TCK
H_TDO
H_VIDALERT#_VR
H_TRST_N
H_PREQ_N
H_PRDY_N
H_VIDSOUT_VR
VCCST_PWRGD_CPU
H_TMS
H_TDI
H_TDO
H_PWRGD
H_PROCHOT#_R
H_PM_DOWN_R
CFG_RCOMP
H_THERMTRIP#
CFG6
CFG7
CFG0
CFG2
CFG4
CFG5
H_THERMTRIP#
CFG9
CPU_VIDALERT#
H_TCK
H_SKTOCC#
VCCST_VCCPLL
3.3VA
VCCST_VCCPLL
VCCST_VCCPLL
H_PECI29
PCH_THERMTRIP#15
H_PM_SYNC15
H_VIDALERT#_VR46
H_VIDSCK_VR46
H_VIDSOUT_VR46
PCH_CPU_BCLK_R_DP18
PCH_CPU_BCLK_R_DN18
PCH_CPU_PCIBCLK_R_DP18
PCH_CPU_PCIBCLK_R_DN18
CPU_24MHZ_R_DP18
CPU_24MHZ_R_DN18
VCCST_PWRGD14
H_PWRGD16
PLTRST_CPU#15
H_PM_DOWN15
H_SKTOCC#15,17
H_PROCHOT_EC29
PCH_PECI15
DDR_VTT_CTRL44
H_PROCHOT#46
JTAG_TDO 16
JTAG_TDI 16
JTAG_TMS 16
JTAG_JTAGX 16
JTAG_TRST# 20
Title
Size Document Number Rev
Date: Sheet
of
6-71-N35T0-D01
1.0
[03] Processor 2/6-JTAG,CLK,CFG
A3
357Thursday, September 20, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Rev
Date: Sheet
of
6-71-N35T0-D01
1.0
[03] Processor 2/6-JTAG,CLK,CFG
A3
357Thursday, September 20, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Rev
Date: Sheet
of
6-71-N35T0-D01
1.0
[03] Processor 2/6-JTAG,CLK,CFG
A3
357Thursday, September 20, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
R95
*20mil_short_04
R121 *1K_04
R496 220_04
R89
*20mil_short_04
R94 *100_04
R495 499_1%_04
R497 56.2_1%_04
R92
*20mil_short_04
R117 *1K_04
R93
*20mil_short_04
U43E
3H993921-4M41-02H
PN = 6-86-25B51-001
lga1151
5 OF 12
VCCST_PWRGD
U2
PM_SYNC
E8
PM_DOWN
D8
PECI
G7
VIDSOUT
E40
DDR_VTT_CNTL
AC36
CFG_18
G18
CFG_19
F18
PROC_TCK
F11
CFG_0
H15
PROC_TDO
H13
THERMTRIP#
D11
CFG_1
F15
PROC_TRST#
F12
PROC_SELECT#
AB36
CFG_2
F16
SKTOCC#
AC38
CFG_RCOMP
M11
CFG_3
H16
PROC_PREQ#
B9
CFG_4
F19
CFG_5
H18
CFG_10
F17
RESET#
E7
BCLKN
W4
CLK24N
J9
CFG_11
H17
CFG_6
G21
PROCPWRGD
F8
VIDSCK
E38
BPM#_0
D16
PCI_BCLKN
W2
CFG_7
H20
CFG_12
G20
BPM#_1
D17
BCLKP
W5
CLK24P
K9
CFG_8
G16
BPM#_2
G14
CFG_13
F20
PCI_BCLKP
W1
BPM#_3
H14
CFG_14
F21
CFG_9
E16
PROCHOT#
C39
CFG_15
H19
PROC_TDI
G12
CFG_16
E14
CATERR#
D13
PROC_PRDY#
B10
CFG_17
F14
PROC_TMS
F13
VIDALERT#
E39
C417
47p_25V_NPO_02
R97 20_1%_04
R96
*20mil_short_04
R115 *1K_04
R91 51_04
R129 *1K_04
R498 100_1%_04
R501 49.9_1%_04
R505 *10K_04
R114 *1K_04
R120 1K_04
R90 *0_04
R499
1K_04
R113 6.04K_1%_04
R502
*100K_04
R504 10K_04
Q28
2SK3018S3
G
DS
R119 2.74K_1%_04
R118 *1K_04
R88
*20mil_short_04
R84 620_06
R87 1K_1%_04
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