5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
N350TW
non-VPRO
U53
6-03-00219-030
6-03-00219-031
Q370 MP
H370 MP
U40
I219LM MP
I219V MP
N350TV
VPRO
U55
U54
GIGA LAN (INTEL LAN I219)
6-03-00370-0F2
6-03-00370-0F0
SB
LAN
ME+Bios
W25Q128JVSIQ
6-04-25128-A74
MX25L25673GM2I-08G
6-04-XXXXX-XXX
N/A
LAN i219
The 10Kohm pull-up resistor of CLK_REQ_N is required
to either 3.3V Suspend (5, 6, 7) or Core (2) rail,
depending on the power well of PCH's input PCIECLKRQx#
buffer. See Platform Design Guide for more details
SMBUS PULL-UP OPTIONS
100KHz/400KHz 2.2Kohm
SMBUS SPEED
1MHz(Defaul setting) 499ohm
NOTE: Default SMBus
Address is 0xC8
NOTE: LANWAKE_N must be
connected to PCH's GPIO27.
NOTE: LAN_DISABLE_N must be connected
to PCH's GPIO12/LAN_PHY_PWR_CTRL.
This GPIO12 pin must be set as
"LAN_PHY_PC" function through FITC
tool.
DESIGN NOTE: PCH's LANPHYPC output
does not require pull-up. Resistors are no-stuff (for testing
purpose only).
暣⭡ῤ
BY
⮎㷔
DESIGN NOTE: C7 & C8 value may vary depending on the
actual Cstray of the board. Cstray is varied because
specific board stack-up, layout, etc. For examples:
Using Cload=18pF Crystal part, if Cstray=7pF then
C7=C8=22pF and if Cstray=6pF then C7=C8=24pF.
Cload=[(C7*C8)/(C7+C8)] + Cstray.
Each design should measure the crystal’s ppm to make
sure it is within the I217 Specification.
Crystal
㓡䓐
5032 SIZE
6-22-25R00-1BV
6-22-25R00-1B4
6-22-25R00-1B5
Keep
short
and wide
NOTE: Total requirement Cout>=20uF. ESR<50mohm.
LAYOUT NOTE: Place L, C*3 and R close to PHY
modify,0510 max
modify,0510 max
modify,0510 max
del,0520 max
modify,0605 max
modify,0514 max
ME+Bios+EC
N/A
LAN_DISABLE_N
LANWAKE_N
LAN_JTAG_TDI
LAN_JTAG_TDO
LAN_XTAL_OUT
RES_BIAS
LAN_TEST_EN
LAN_XTAL_IN
PCIE_RXN5_C_GLAN
PCIE_RXP5_C_GLAN
CTRL_0P9
0.9V_LAN_M
LAN_MDIN0
LAN_MDIP0
LAN_MDIN1
LAN_MDIP1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3
SVR_EN_N
LAN_JTAG_TCK
LAN_JTAG_TMS
3.3V_LAN
VDD3
VDD3
VDD3
3.3V_LAN
3.3V_LAN
3.3V_LAN
PM_LANPHY_EN16
LAN_WAKEUP#16,28,29
PCIE_RXP5_IGLAN14
SML0_DATA16
PCIE_RXN5_IGLAN14
PCIE_TXP5_IGLAN14
SML0_CLK16
IGLAN_CLKREQ#18
CLK_PCIE_IGLAN#18
PCIE_TXN5_IGLAN14
CLK_PCIE_IGLAN18
BUF_PLT_RST#14,24,27,29,35,38,39,40
LAN_MDIN3 23
LAN_MDIP2 23
LAN_MDIP3 23
LAN_MDIN1 23
LAN_MDIN0 23
LAN_MDIP1 23
LAN_MDIP0 23
LAN_MDIN2 23
Title
Size Document Number Rev
Date: Sheet
of
6-71-N35T0-D01
1.0
[22] INTEL LAN i219-LM
A3
22 57Thursday, September 20, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Rev
Date: Sheet
of
6-71-N35T0-D01
1.0
[22] INTEL LAN i219-LM
A3
22 57Thursday, September 20, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Rev
Date: Sheet
of
6-71-N35T0-D01
1.0
[22] INTEL LAN i219-LM
A3
22 57Thursday, September 20, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
R448 *10K_04
C380
10p_25V_NPO_02
C61
0.1u_6.3V_X5R_02
C393 0.1u_10V_X7R_04
R454 4.7K_04
R52
3.01K_1%_04
R59 4.7K_04
R56
1K_04
R440 0_04
R451 0_04
C391 1u_6.3V_X5R_02
R438 *10K_04
X2
FSX3L 25MHz
1 2
34
R443 *10K_04
C394 0.1u_10V_X7R_04
R435 *499_1%_04
.
L13
SWF2520CF-4R7M-M
C382
22u_6.3V_X5R_06
R434 0_04
C57
0.1u_6.3V_X5R_02
R449 *10K_04
C59
0.1u_6.3V_X5R_02
C383
*10u_6.3V_X5R_06
PCIE
MDI
SMBUS
JTAG LED
U40
i219-LM
RSVD_VCC3P3
1
LANWAKE_N
2
LAN_DISABLE_N
3
VDD3P3_4
4
VDD3P3_5
5
SVR_EN_N
6
CTRL_0P9
7
VDD0P9_47
47
XTAL_OUT
9
XTAL_IN
10
VDD0P9_37
37
RBIAS
12
MDI_PLUS0
13
MDI_MINUS0
14
VDD3P3_15
15
VDD0P9_46
46
MDI_PLUS1
17
MDI_MINUS1
18
VDD3P3_19
19
MDI_PLUS2
20
MDI_MINUS2
21
VDD0P9_43
43
MDI_PLUS3
23
MDI_MINUS3
24
LED2
25
LED0
26
LED1
27
SMB_CLK
28
VDD3P3_29
29
TEST_EN
30
SMB_DATA
31
JTAG_TDI
32
JTAG_TMS
33
JTAG_TDO
34
JTAG_TCK
35
PE_RST_N
36
VDD0P9_16
16
PETp
38
PETn
39
VDD0P9_40
40
PERp
41
PERn
42
VDD0P9_22
22
PE_CLKP
44
PE_CLKN
45
VDD0P9_11
11
VDD0P9_8
8
CLK_REQ_N
48
GND_EPAD
49
R450
10K_04
R452 0_04
R437 *499_1%_04
R446 *4.7K_04
C381
10p_25V_NPO_02
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