Clevo P775DM2-G - System Power On Sequence Diagram

Schematic Diagrams
Power On Sequence B - 71
B.Schematic Diagrams
Power On Sequence
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCST
VCCST_PWRGD >1ms
VDDQ <25ms
VCCIO
>100ns
VCCSA >100ns
PROCPWRGD
>1ms
VCCPLL
PCH_PWROK >0
DDR_VTT_CNTL
DDR_VTT
<35us
<100ns
194ms
PWR_SW#
VDD5
0.86ms
1.96ms
PLTRST#
1.28ms
1.48ms
0.38ms
1.96ms
1.24ms
0.68ms
5V
SLP_SUS#
30.4ms
3.3VA
1.0VA
RSMRST# (=DPWROK)
0.8ms
4.6ms
50.6ms
1.4ms
0.48ms
VCCST_VCCPLL
VDDQ
2.5V
0.72ms
VCCIO_EN
VCCIO_PWRGD
VCCSA
1ms
2.32ms
0.2ms
PM_PCH_PWROK (=VCCST_PWRGD)
2.32ms
35us
H_PWRGD
284ms
2.68ms
PWR_BTN#
174ms
Power on
5VS_2
VCCIO
5VS
EC DELAY_PWRGD (=PM_PWROK)
RTCRST#
SUSC#
3.3VS
ALL_SYS_PWRGD
DD_ON
SUSB#
VR_READY
3.3V
DDR_VTT_CNTL
VTT_MEM
1.36ms
2.32ms
VCORE
2.6ms
100ms
DESIGN GUIDE
天㯪
118ms
Title
Size Document Number Rev
Date: Sheet
of
<Doc> <RevCode>
<Title>
Custom
70 70Thursday, July 14, 2016
Title
Size Document Number R e v
Date : Sheet
of
<Doc> <RevCode>
<Title>
Custom
70 70Thursday, July 14, 2016
Title
Size Document Number R e v
Date : Sheet of
<Doc> <RevCode>
<Title>
Custom
70 70Thursday, July 14, 2016
Sheet 70 of 70
Power On
Sequence