H_PROCHOT#
H_CPUPWRGD_R
PM_DR AM_PW RGD20
1.5V6,9, 10,35,37, 38
H_PECI34
H_PM_SYNC20
CAD Note: Capacitor
need to be placed
close to buffer
output pin
TRACE WIDTH 10MIL, LENG TH <500MILS
H_CPUPWRGD_R
Processor Pull downs
PU/PD for JTAG signals
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
U31B
Iv y Bridge_rPGA_2DPC_Rev 0p61
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_DRAMRST#
R8
SM_RCOMP[0]
AK1
BCLK#
A27
BCLK
A28
DPLL_R EF_CLK#
A15
DPLL_R EF_CLK
A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THER MTRIP#
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRD Y#
AP29
PREQ #
AP27
TC K
AR26
TMS
AR27
TRST#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SYNC
AM34
SKTOCC#
AN34
PRO C_SELEC T#
C26
UNCOREPWRGOOD
AP33
1.05VS_VTT2,5, 23,24,25, 37,39,40
CLK_BCLK 19
1.5VS_CPU6,35
3.3V2,6, 11,16,18, 19,20,22, 23,24,25, 27,28,29 ,30,35,37,38,39, 40,42
CLK_DP 19
CLK_DP# 19
CLK_BCLK# 19
D RAMR ST_ CN TR L 6, 19
3.3VS9,10, 11,12,18, 19,20,21, 22,23,24,25, 27,28,30, 31,32,33,34, 35,40
H_CPUPWRGD23
H_PR OCHOT#_EC34
XDP_DBR_R
H_PROCHOT#40,42
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
XD P _T R S T #
XD P _T C L K
VDDPWRGOOD_R
H_PROCHOT#_R
XD P _T MS
CPU_DRAMRST#
XDP_PREQ#
XD P _T D I _ R
XD P _T D O _ R
R341 * 10mil_short _04
R199 *0_04
C151
47p_50V_NPO_04
R198
1K_04
R87
62_04
R339 1K_04
R342 * 10mil_short _04
R98 *10mil_short_04
R34310K_04
Q5
MTN 7 00 2Z H S3
G
DS
TRACE WIDTH 10MIL, LE NGTH <500MILS
Processor Pull up
H_CPUPWRGD
R99 56_1%_04
C601
*0. 1u_16V_Y5V_04
R363 51_04
R138 200_1%_04
R340 * 10mil_short _04
R354 51_04
R173 130 _1%_04
C433
0.047u_10V_X7R_04
R168
200_1%_04
R362 51_04
R384 140_1%_04
R200 1K_0 4
Q13
MTN7002ZHS3
G
DS
R361 51_04
R137 25. 5_1%_04
R355 *51_04
H_PM_SYNC_R
R449
4.99K_1%_04
R174 *10mil_short _04
R348 51_04
R79
100K_04
If PROCHOT# is not used,
then it must be terminated
with a 56-£[ +-5% pull-up
resistor to 1.05VS_VTT .
DDR3 Compensation Signals
BUF_CPU_RST#
SM_RCOMP_1
SM_RCOMP_0
SM_RCOMP_2
DDR 3_DRAMRST# 9,10
H_SNB_IVB#23
H_ THR MTR IP#23
XDP_BPM0_R
XDP_BPM1_R
XDP_BPM2_R
XDP_BPM4_R
XDP_BPM3_R
XDP_BPM5_R
XDP_BPM6_R
XDP_BPM7_R
XD P _P R D Y #
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
PMSY S_PWR GD_BU F
H_THRMTRIP#_R
S3 circuit:- DRAM PWR GOOD logic
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
1.5VS_CPU
1.5V
1.05VS_VTT
3.3VS
1.05VS_VTT
BUF_CPU_RST#
R356
75_04
R336
100K_04
S
D
G
Q18B
L2N7002D W1T1G
5
34
H_PECI_R
S
D
G
Q18A
L2N7002D W1T1G
2
61
R357
43_1%_04
CPU_DRAMRST#
R337
10K_04
1.05VS_VTT
3.3VS
Buffered reset to CPU
PL T_R ST#12,22,28
S3 circuit:- DRAM_RST# to memory
should be high during S3
XDP_DBR_R
H_CATERR#
XDP_TRST#
H_SNB_IVB#
XD P _T D O _ R
XD P _T C L K
XD P _T D I _ R
XD P _T MS
XDP_PREQ#
PMSY S_PWR GD_B UF
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