Cmsemicon SC8F577 Series - Page 5

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SC8F577x
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15.1 THE BLOCK DIAGRAM OF PGA ..................................................................................................................................... 100
15.2 THE RELATED REGISTER OF PGA ................................................................................................................................ 101
15.3 THE OPERATION FLOW OF PGA ................................................................................................................................... 101
16. UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS TRANSMITTER (USART) ............. 102
16.1 USART ASYNCHRONOUS MODE ................................................................................................................................. 104
16.1.1 USART Asynchronous Generator ....................................................................................................................... 104
16.1.1.1 Enable Transmit ..................................................................................................................................... 104
16.1.1.2 Transmit Data ......................................................................................................................................... 105
16.1.1.3 Transmit Interrupt ................................................................................................................................... 105
16.1.1.4 TSR Status ............................................................................................................................................. 105
16.1.1.5 Transmit 9-bit Character ......................................................................................................................... 105
16.1.1.6 Configure Asynchronous Transmit.......................................................................................................... 106
16.1.2 USART Asynchronous Receiver ......................................................................................................................... 107
16.1.2.1 Enable Receiver ..................................................................................................................................... 107
16.1.2.2 Receive Data .......................................................................................................................................... 107
16.1.2.3 Receive Interrupt .................................................................................................................................... 108
16.1.2.4 Receive Frame Error .............................................................................................................................. 108
16.1.2.5 Receive Overflow Error ........................................................................................................................... 108
16.1.2.6 Receive 9-bit Character .......................................................................................................................... 108
16.1.2.7 Asynchronous Receive Configuration ..................................................................................................... 109
16.2 CLOCK PRECISION FOR ASYNCHRONOUS OPERATIONS .................................................................................................. 110
16.3 USART RELATED REGISTER ....................................................................................................................................... 110
16.4 USART BAUD RATE GENERATOR (BRG) ..................................................................................................................... 112
16.5 USART SYNCHRONOUS MODE ................................................................................................................................... 112
16.5.1 Synchronous Master Control Mode ..................................................................................................................... 113
16.5.1.1 Master Control Clock .............................................................................................................................. 113
16.5.1.2 Clock Polarity .......................................................................................................................................... 113
16.5.1.3 Synchronous Master Control Transmit ................................................................................................... 114
16.5.1.4 Synchronous Master Control Transmit Configuration ............................................................................. 114
16.5.1.5 Synchronous Master Control Receive .................................................................................................... 115
16.5.1.6 Slave Clock ............................................................................................................................................. 115
16.5.1.7 Receive Overflow Error ........................................................................................................................... 116
16.5.1.8 Receive 9-bit Character .......................................................................................................................... 116
16.5.1.9 Synchronous Master Control Receive Configuration .............................................................................. 116
16.5.2 Synchronous Slave Mode ................................................................................................................................... 117
16.5.2.1 USART Synchronous Slave Transmit ..................................................................................................... 117
16.5.2.2 Synchronous Slave Transmit Configuration ............................................................................................ 117
16.5.2.3 USART Synchronous Slave Receive ...................................................................................................... 117
16.5.2.4 Synchronous Slave Receive Configuration ............................................................................................. 118
17. SPI MODE ....................................................................................................................... 119
17.1 SPI MODE GENERAL .................................................................................................................................................. 119
17.2 SPI RELATED REGISTERS ........................................................................................................................................... 120
17.3 SPI WORKING PRINCIPLE ........................................................................................................................................... 122
17.4 ENABLE SPI I/O ......................................................................................................................................................... 124
17.5 MASTER CONTROL MODE ........................................................................................................................................... 124
17.6 SLAVE MODE ............................................................................................................................................................. 126
17.7 SLAVE SYNCHRONOUS SELECTION ............................................................................................................................... 126
17.8 SLEEP OPERATION ..................................................................................................................................................... 127
17.9 EFFECT OF RESET ...................................................................................................................................................... 127