7. BIOS Setup
56
SPC-8520-LA , SPC-8521-LA
Description Choice
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM
at F0000h-FFFFFh, resulting in better system
performance. However, if any program writes to this
memory area, a system error may result.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at
C0000h to CFFFFh, resulting in better video performance.
However, if any program writes to this memory area, a
system error may result.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter
ROM. When this area is reserved, it cannot be cached. The
user information of peripherals that need to use this area of
system memory usually discusses their memory
requirements.
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to
support delay transactions cycles. Select Enabled to
support compliance with PCI specification version 2.1.
Delay Prior to Thermal
Select the interval to setup the delay timer for CPU
Thermal-Throttling.
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