12. Block Diagram (MB95770M Series)
Reset with LVD
Flash with security function
(60/36/20 Kbyte)
F
2
MC-8FX CPU
RAM (2048/1024/512 bytes)
Interrupt controller
Oscillator
circuit
CR
oscillator
Clock control
On-chip debug
Wild register
Watch counter
External interrupt
UART/SIO ch. 0
8/16-bit composite timer ch. 0
8/12-bit A/D converter
16-bit reload timer ch. 0
8/16-bit composite timer ch. 1
UART/SIO ch. 1
I
2
C bus interface ch. 0
8/16-bit PPG ch. 0
8/16-bit PPG ch. 1
Port Por t
PF2
*1
/RST
*2
PF0/X0
*2
PF1/X1
*2
PG1/X0A
*2
PG2/X1A
*2
P00/INT00 to P07/INT07
C
P14/UCK0
P11/UO0
P10/UI0
P05/UCK1
P03/UO1
P04/UI1
UART/SIO ch. 2
P02/UCK2
P00/UO2
P01/UI2
P20/PPG00
P21/PPG01
P16/PPG10
P15/PPG11
P22
*1
/SCL
P23
*1
/SDA
P12
*1
/DBG
P01/TO00
P13/TO01
P14/EC0
P00/AN00 to P07/AN07
P13/ADTG
LCDC
(4 COM or 8 COM)
P90/V4 to P93/V1
PA0/COM0 to PA3/COM3
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC3/SEG05
P60/SEG06 to P67/SEG13
PE0/SEG14 to PE7/SEG21
P07/SEG22 to P00/SEG29
P16/SEG30, P15/SEG31
P90/V4 to P93/V1
4 COM mode:
8 COM mode:
PA0/COM0 to PA7/COM7
PB0/SEG00, PB1/SEG01
PC0/SEG02 to PC3/SEG05
P60/SEG06 to P67/SEG13
PE0/SEG14 to PE7/SEG21
P07/SEG22 to P02/SEG27
PE5/TO11
PE6/TO10
PE7/EC1
Comparator ch. 0 P20/CMP0_N
P21/CMP0_P
P17/CMP0_O
P14/TI0
P10/TO0
Vcc
Vss
*1:
*2:
*3:
P12, P22, P23 and PF2 are N-ch open drain pins.
Software option
When the event counter operation mode is enabled, 8/16-bit composite timer ch. 1 and 16-bit reload timer ch. 0 can be used as an event counter.
Internal bus
*3
To Next Page
Loading...
