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Cypress MB95710M Series - Port 1

Cypress MB95710M Series
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MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 56 of 172
Operation in stop mode and watch mode
If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 reg-
ister value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. How-
ever, if the interrupt input is enabled for the external interrupt (INT00 to INT07), the input is enabled and not
blocked.
If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
Operation as an analog input pin
Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin
in the AIDRL register to “0”.
For a pin shared with other peripheral functions, disable the output of such peripheral functions.
Operation as an external interrupt input pin
Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”.
For a pin shared with other peripheral functions, disable the output of such peripheral functions.
The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt,
disable the external interrupt function corresponding to that pin.
18.2 Port 1
Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”.
18.2.1 Port 1 configuration
Port 1 is made up of the following elements.
General-purpose I/O pins/peripheral function I/O pins
Port 1 data register (PDR1)
Port 1 direction register (DDR1)
Port 1 pull-up register (PUL1)
18.2.2 Block diagrams of port 1
P10/UI0 pin
This pin has the following peripheral function:
UART/SIO ch. 0 data input pin (UI0)

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