Cypress MB95710M Series - Page 55

MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 54 of 172
• Block diagram of P01/INT01/AN01/SEG36/UI2 and P04/INT04/AN04/SEG33/UI1
18.1.3 Port 0 registers
• Port 0 register functions
• Correspondence between registers and pins for port 0
Register
abbreviation
Data Read
Read by read-modify-write
(RMW) instruction
Write
PDR0
0 Pin state is “L” level. PDR0 value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDR0 value is “1”. As output port, outputs “H” level.
DDR0
0 Port input enabled
1 Port output enabled
AIDRL
0 Analog input enabled
1 Port input enabled
Correspondence between related register bits and pins
Pin name P07 P06 P05 P04 P03 P02 P01 P00
PDR0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0DDR0
AIDRL
PDR0
Pin
PDR0 read
PDR0 write
Executing bit manipulation instruction
DDR0 read
DDR0 write
AIDRL read
AIDRL write
DDR0
AIDRL
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
(INT01 and INT04)
Peripheral function output enable
Peripheral function output
A/D analog input
Internal bus
LCD output
LCD output enable
CMOS