Cypress MB95710M Series - Port 5 (MB95710 M)

MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 65 of 172
18.4.3 Port 4 registers
• Port 4 register functions
• Correspondence between registers and pins for port 4
18.4.4 Port 4 operations
• Operation as an output port
• A pin becomes an output port if the bit in the DDR4 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR4 register to external pins.
• If data is written to the PDR4 register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDR4 register returns the PDR4 register value.
• To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable
register 5 (LCDCE5:SEG[21:18]) to “0” to select the general-purpose I/O port function, and then set the port input
control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”.
• Operation as an input port
• A pin becomes an input port if the bit in the DDR4 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR4 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR4 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR4 register, the PDR4 register value is returned.
• To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable
register 5 (LCDCE5:SEG[21:18]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit
in the LCDCE1 register to “1”.
• Operation as an LCDC segment output pin
• Set the bit in the DDR4 register corresponding to an LCDC segment output pin to “0”.
• To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function
select bit in the LCDC enable register 5 (LCDCE5:SEG[21:18]) to “1” to select the LCDC segment output function,
and then set the PICTL bit in the LCDCE1 register to “1”.
• Operation at reset
If the CPU is reset, all bits in the DDR4 register are initialized to “0” and port input is enabled.
Register
abbreviation
Data Read
Read by read-modify-write
(RMW) instruction
Write
PDR4
0 Pin state is “L” level. PDR4 value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDR4 value is “1”. As output port, outputs “H” level.
DDR4
0 Port input enabled
1 Port output enabled
Correspondence between related register bits and pins
Pin name----P43P42P41P40
PDR4
----bit3bit2bit1bit0
DDR4