Cypress MB95710M Series - Page 76

MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 75 of 172
• Block diagram of PA0/COM0, PA1/COM1, PA2/COM2, PA3/COM3, PA4/COM4, PA5/COM5, PA6/COM6 and
PA7/COM7
18.8.3 Port A registers
• Port A register functions
• Correspondence between registers and pins for port A
Register
abbreviation
Data Read
Read by read-modify-write
(RMW) instruction
Write
PDRA
0 Pin state is “L” level. PDRA value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDRA value is “1”. As output port, outputs “H” level.
DDRA
0 Port input enabled
1 Port output enabled
Correspondence between related register bits and pins
Pin name PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PDRA
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DDRA
PDRA
Pin
PDRA read
PDRA write
Executing bit manipulation instruction
DDRA read
DDRA write
DDRA
0
1
Stop mode, watch mode (SPL = 1)
LCD output
Internal bus
LCD output enable