MB95710M Series
MB95770M Series
Document Number: 002-09307 Rev. *D Page 88 of 172
• Block diagram of PG1/X0A and PG2/X1A
18.13.3 Port G registers
• Port G register functions
• Correspondence between registers and pins for port G
Register
abbreviation
Data Read
Read by read-modify-write
(RMW) instruction
Write
PDRG
0 Pin state is “L” level. PDRG value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDRG value is “1”. As output port, outputs “H” level.
DDRG
0 Port input enabled
1 Port output enabled
PULG
0 Pull-up disabled
1 Pull-up enabled
Correspondence between related register bits and pins
Pin name-----PG2PG1-
PDRG
-----bit2bit1-DDRG
PULG
PDRG
Pin
PDRG read
PDRG write
Executing bit manipulation instruction
DDRG read
DDRG write
PULG read
PULG write
DDRG
PULG
0
1
Stop mode, watch mode (SPL = 1)
Hysteresis
Pull-up
Internal bus
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