Danfysik SYSTEM 9100 - Page 51

MAGNET POWER SUPPLY SYSTEM 9100
51
DANFYSIK A/S - DENMARK.
Bipolar block diagram:
5V
Uni/Bipolar Mode
Inverter
+24VDC_S
/OFF RES
+24VDC_S /1,6A
±15V
+5V
Ethernet controller
BIPOLAR OUTPUT STAGE
3.3V
10VDC 125A
I SET OPTO
ISOLATION
Peltier Control
Optional SERIAL SPI INTERFACE
I/O SPI PORT
AUX POWER FAN CONTROL
AUX POWER LOOP & CPU
±15V
±15VDC_C /1,2A
H8 uP
LOCAL M-PANEL
LCD DISPLAY 240x64 DOT KEYBOARD
OPTION
DC/DC PSU
TRIG X9
J101
BUFFER
RAM
POLARITY X8
CONN.
D-SUB 25
DC
MAIN POWER INPUT 3PHASE
CONN. SCREW TERMINAL
OPTO
ATmega 128
SYNC A 0°
D-SUB 9
SYNC B 180°
19 BIT D/A Uni & BiPo, I set
REMOTE RS232/RS422 X7
16 BIT A/D
+5VDC_C
Differential Input (Io, Vo, Iset)
SMPS GALVANIC ISOLATED AUX POWER
±15VDC_C
D-SUB 25
REF. A/D D/A
POLARITY SWITCH
OPTO
EMC FILTER
SOFT START MODULE
X414
AC INPUT FILTER
RECTIFIER 3PHASE U V W
- +
OVERCURRENT BREAKER (FRONT OPPERATED)
I >
1 2
FILTER
Ext/Int SPI interface Select & Detect
+12V /0.1A
PARALLEL INTERFACE X108
ON /OFF SUM_INTL
OPTO STATUS/CONTROL
16 BIT D/A V set
+15VDC_P /2A
ON
TRIG IN/OUT
ROM
Output Current
INTERLOCK & ON/OFF CONTROL
CONN.
-5V /0.1A
AUX POWER PCB
Output Voltage
5V to 3.3V
supply
Module Fail, OPTO Over Temperature, OPTO
CONN.
DCCT I HEAD
CONN.
X5
SLEW RATE LIMIT
OUTPUT MODULE
NO. 1
Vo
NO. 2 to 3 DC/DC SMPS
Io
FANS
I-LOOP, CONTROL, INTERLOCK PCB
ENABLE I-SET
X24
+15VDC_P ±15VDC_C
AUX POWER FOR DC/DC PRIMARY SIDE
DC/DC SMPS
D-SUB 25
SYNC
X25
DIFFERENTIAL AMPLIFIER
Relay Interface X414
CONTROL POWER INPUT 1PHASE
X1
REGULATION I LOOP V LOOP
X1
OPTIONAL
DIFFERENTIAL AMPLIFIER
0-10V
SOFT START
Iset Vout Iout
0-10V
Iset Vset
Optional X6 For local M-Panel
CONN.
PWM
ETHERNET Module
Overcurrent, Ground leak
J101
CONN.
PWM
Vout
AC LINE MONITOR (AC OK)
10 BIT
A/D
Ext. intl X12
SYNC
CONN.
±12VDC_C /0,1A